Integrated circuit tester including at least one quasi-autonomous test instrument

Claim 2

An integrated circuit tester for testing an integrated circuit device (DUT) having a plurality of signal pins, said integrated circuit tester including: a plurality of tester modules having respective signal terminals for connection to respective signal pins of the DUT, each tester module having a plurality of operating modes, a means for providing a clock signal, a quasi-autonomous test instrument for performing an acquisition task, said test instrument including a state machine, a command stack for storing commands which specify parameters of the acquisition task, an acquisition device having at least one terminal for connection to a pin of the DUT for acquiring a value of a variable from the DUT in accordance with the defined parameters of the acquisition task, and an acquisition memory for temporarily storing acquired values and making the acquired values available after the test, and a sequencer means coupled operatively to the tester modules for causing the modules to execute a test and coupled operatively to the quasi-autonomous test instrument for supplying a trigger to the test instrument, and wherein the state machine is responsive to the trigger to initiate performance of the acquisition task by reading a command from the command stack and performing the acquisition task in accordance with the parameters specified in the command under control of the clock signal.

Claim 3

A tester according to claim 1, wherein said quasi-autonomous test instrument is a current measuring power supply including a power supply amplifier and a current measurement device for measuring current supplied to a power supply pin of the DUT by the power supply amplifier.

Claim 4

A tester according to claim 2, wherein the acquisition device includes a current sensing resistor means and a digitizing means for sensing and digitizing voltage drop across the current sensing resistor means.

Claim 5

A tester according to claim 3, wherein the digitizing means comprises a differential amplifier and an analog-to-digital converter.

Claim 6

A tester according to claim 4, wherein the commands stored by the command stack specify sampling rate of the digitizer.

Claim 7

A tester according to claim 4, further comprising a low pass filter connected between the differential amplifier and the analog-to-digital converter, and wherein the commands stored by the command stack specify cutoff frequency of the low pass filter.

Claim 8

A tester according to claim 2, wherein the commands stored by the command stack specify sensitivity of the current measurement device.

Claim 9

A tester according to claim 1, wherein the commands stored by the command stack specify a start delay and the state machine is responsive to the start delay to delay acquisition of values until the start delay has elapsed.

Claim 10

An integrated circuit tester for testing an integrated circuit device (DUT) having a plurality of signal pins, said integrated circuit tester including: a plurality of tester modules each having a signal terminal for connection to a signal pin of the DUT, a means for providing a clock signal, a first quasi-autonomous test instrument for performing a first acquisition task, said first test instrument including a state machine, a command stack for storing commands which specify parameters of the first acquisition task, an acquisition device having at least one terminal for connection to a first pin of the DUT for acquiring a value of a variable from the DUT in accordance with the defined parameters of the first acquisition task, and an acquisition memory for temporarily storing acquired values and making the acquired values available after the test, a second quasi-autonomous test instrument for performing a second acquisition task, said second test instrument including a state machine, a command stack for storing commands which specify parameters of the second acquisition task, an acquisition device having at least one terminal for connection to a second pin of the DUT for acquiring a value of a variable from the DUT in accordance with the defined parameters of the second acquisition task, and an acquisition memory for temporarily storing acquired values and making the acquired values available after the test, a sequencer means coupled operatively to the tester modules for causing the modules to execute a test and coupled operatively to the first and second test instruments for supplying triggers to the first and second test instruments, and wherein the state machine of the first test instrument is responsive to a trigger received by the first test instrument to initiate performance of the first acquisition task by reading a command from the command stack of the first test instrument and performing the first acquisition task in accordance with the parameters specified in the command under control of the clock signal and the state machine of the second test instrument is responsive to a trigger received by the second test instrument to initiate performance of the second acquisition task by reading a command from the command stack of the second test instrument and performing the second acquisition task in accordance with the parameters specified in the command under control of the clock signal.

Claim 11

An integrated circuit tester for testing an integrated circuit device (DUT) having a plurality of signal pins, said integrated circuit tester including: a plurality of tester modules each having a signal terminal for connection to a signal pin of the DUT, a means for providing a clock signal, a first quasi-autonomous test instrument for performing a first acquisition task, said first test instrument including a state machine, a command stack for storing commands which specify parameters of the first acquisition task, an acquisition device having at least one terminal for connection to a first pin of the DUT for acquiring a value of a variable from the DUT in accordance with the defined parameters of the first acquisition task, and an acquisition memory for temporarily storing acquired values and making the acquired values available after the test, a second quasi-autonomous test instrument for performing a second acquisition task, said second test instrument including a state machine, a command stack for storing commands which specify parameters of the second acquisition task, an acquisition device having at least one terminal for connection to a second pin of the DUT for acquiring a value of a variable from the DUT in accordance with the defined parameters of the second acquisition task, and an acquisition memory for temporarily storing acquired values and making the acquired values available after the test, a sequencer means coupled operatively to the tester modules for causing the modules to execute a test and coupled operatively to the first and second test instruments for supplying triggers to the first and second test instruments, and wherein the state machine of the first test instrument is responsive to a trigger received by the first test instrument to initiate performance of the first acquisition task by reading a command from the command stack of the first test instrument and performing the first acquisition task in accordance with the parameters specified in the command under control of the clock signal and the state machine of the second test instrument is responsive to a trigger received by the second test instrument to initiate performance of the second acquisition task by reading a command from the command stack of the second test instrument and performing the second acquisition task in accordance with the parameters specified in the command under control of the clock signal.

Claim 12

A tester according to claim 1, comprising a plurality of quasi-autonomous test instruments for performing respective acquisition tasks and each including a state machine, a command stack, an acquisition device and an acquisition memory, and wherein each instrument is responsive to a common master clock, whereby the instruments operate synchronously.

Claim 13

An integrated circuit tester for testing an integrated circuit device (DUT) having a plurality of signal pins, said integrated circuit tester including: a plurality of tester modules each having a signal terminal for connection to a signal pin of the DUT, a means for providing a clock signal, first and second quasi-autonomous test instruments for performing first and second acquisition tasks respectively, each instrument including a state machine, a command stack for storing commands which specify parameters of the acquisition task, an acquisition device having at least one terminal for connection to a pin of the DUT for acquiring a value of a variable from the DUT in accordance with the defined parameters of the acquisition task, and an acquisition memory for temporarily storing acquired values and making the acquired values available after the test, and a sequencer means coupled operatively to the tester modules for causing the modules to execute a test and coupled operatively to the first and second quasi-autonomous test instruments for supplying first and second triggers to the first and second test instruments respectively, and wherein the state machine of the first test instrument is responsive to the first trigger to initiate performance of the first acquisition task by reading a command from the command stack and performing the acquisition task in accordance with the parameters specified in the command under control of the clock signal; and the state machine of the second test instrument is responsive to the second trigger to initiate performance of the second acquisition task by reading a command from the command stack and performing the acquisition task in accordance with the parameters specified in the command under control of the clock signal.

Claim 14

An integrated circuit tester for testing an integrated circuit device (DUT) having a plurality of signal pins, said integrated circuit tester including: a plurality of tester modules each having a signal terminal for connection to a signal pin of the DUT, a means for providing a clock signal, first and second quasi-autonomous test instruments for performing first and second acquisition tasks respectively, each instrument including a state machine, a command stack for storing commands which specify parameters of the acquisition task, an acquisition device having at least one terminal for connection to a pin of the DUT for acquiring a value of a variable from the DUT in accordance with the defined parameters of the acquisition task, and an acquisition memory for temporarily storing acquired values and making the acquired values available after the test, and a sequencer means coupled operatively to the tester modules for causing the modules to execute a test and coupled operatively to the first and second quasi-autonomous test instruments for supplying first and second triggers to the first and second test instruments respectively, and wherein the state machine of the first test instrument is responsive to the first trigger to initiate performance of the first acquisition task by reading a command from the command stack and performing the acquisition task in accordance with the parameters specified in the command under control of the clock signal; and the state machine of the second test instrument is responsive to the second trigger to initiate performance of the second acquisition task by reading a command from the command stack and performing the acquisition task in accordance with the parameters specified in the command under control of the clock signal.

Claim 15

A tester according to claim 11, wherein the first and second test instruments are separately responsive to the first and second triggers respectively and both are responsive to a third trigger.

Claim 18

A method according to claim 13, wherein the acquisition task is measuring quiescent current of the DUT.

Claim 19

A method according to claim 13, wherein the acquisition task is measuring dynamic current of the DUT.