Patent US5930596A successfully refreshed from Google Patents.
US5930596A
Expired / Lapsed
US
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Semiconductor component for vertical integration and manufacturing method
Assignee: Infineon Technologies AG
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Filing: 1995-03-07
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Granted: 1999-07-27
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Expires: 2015-03-07
Abstract
Abstract A terminal metallization (8) is applied onto and structured on a layer structure on the upper side of the component, the terminal metallization is applied on the upper side of an insulating layer (7) with an opening on a metallization (6) provided for electrical connection. By filling a hole produced in a covering dielectric with metal, a contact rod (12) seated on this terminal metallization (8) is formed. This contact rod is resiliently movable in a surrounding opening (14) of the component on the free part of the terminal metallization (8) anchored in the layer structure. This enables the reversible contacting of the component to a further component arranged vertically thereto, whereby the planar upper sides lying opposite one another can be brought into intimate contact because the contact rod (12) pressed against a contact (15) of the other component is pressed back into the opening (14) and an adequately firm connection of the contacts is achieved by the spring power of the terminal metallization (8).
Inventors
- 👤 Helmut Klose
- 👤 Werner Weber
- 👤 Emmerich Bertagnolli
- 👤 Siegmar Koppe
- 👤 Holger Hubner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:30
CPC Classifications
H; H10; H10W; H10W72/00; H10W70/00; H10W70/60
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
163 words
A method for manufacturing a semiconductor component, comprising the steps of: in a first step, applying a layer structure defined by an intended functioning of the semiconductor component onto a substrate; in a second step, applying on the layer structure an insulating layer that leaves a region provided for electrical connection free; in a third step, applying and structuring a terminal metallization on the insulating layer; in a fourth step, applying a dielectric surface-wide, over the insulating layer and the metallization; in a fifth step, producing a hole in said dielectric, so that the terminal metallization is uncovered; in a sixth step, filling said hole with a metal for forming a contact rod in a seventh step, removing the dielectric such that the contact rod projects beyond an upper side of the semiconductor component; and in an eighth step, etching an area that surrounds the contact rod such that the contact rod and a portion of the terminal metallization adjacent thereto are uncovered.
Claim 2
Independent Claim
163 words
A method for manufacturing a semiconductor component, comprising the steps of: in a first step, applying a layer structure defined by an intended functioning of the semiconductor component onto a substrate; in a second step, applying on the layer structure an insulating layer that leaves a region provided for electrical connection free; in a third step, applying and structuring a terminal metallization on the insulating layer; in a fourth step, applying a dielectric surface-wide, over the insulating layer and the metallization; in a fifth step, producing a hole in said dielectric, so that the terminal metallization is uncovered; in a sixth step, filling said hole with a metal for forming a contact rod in a seventh step, removing the dielectric such that the contact rod projects beyond an upper side of the semiconductor component; and in an eighth step, etching an area that surrounds the contact rod such that the contact rod and a portion of the terminal metallization adjacent thereto are uncovered.
Claim 3
Dependent Claim
83 words
The method according to claim 1, wherein the fourth step is implemented in that a first dielectric layer, an etch stop layer and a second dielectric layer are applied surface-wide; wherein the fifth step is implemented in that a hole is etched into the first and second dielectric layers and into the etch stop layer, so that the terminal metallization is uncovered; and wherein the seventh step is implemented in that the second dielectric layer is removed down to the etch stop layer.
Claim 4
Dependent Claim
75 words
The method according to claim 1, wherein the method further comprises: providing a further semiconductor component; using the semiconductor component for testing the further semiconductor component; providing the semiconductor components with functional structures adapted to said testing; and bringing the semiconductor components into contact with one another such that the contact rod of the one semiconductor component is pressed against a contact of the further semiconductor component such that an electrically conductive connection is formed.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-07-26 | 2003-01-25 | 2003-07-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-07-26 | 2007-01-25 | 2007-07-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-07-26 | 2011-01-25 | 2011-07-27 | $7700.00 | Window Closed / Lapsed |