Patent JPS6239658A successfully refreshed from Google Patents.
Patent US5929672A successfully refreshed from Google Patents.
US5929672A
Expired / Lapsed
US
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Power on reset circuit and one chip microcomputer using same
Assignee: Rohm Co Ltd
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Filing: 1996-06-13
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Granted: 1999-07-27
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Expires: 2016-06-13
Abstract
Abstract A power-on reset circuit incorporated in a semiconductor device, such as a one-chip microcomputer, includes a first capacitor and a second capacitor each having one of its electrodes grounded, a first switch circuit connecting the other electrode of the first capacitor to a voltage source, a second switch circuit connecting the electrode of the first capacitor connected to the voltage source to the other electrode of the second capacitor, a voltage detecting circuit which outputs a reset-releasing signal when the voltage of the second capacitor reaches a specified voltage level, and a discharge circuit having a first resistor and a diode connected in series between the second capacitor and the voltage source for discharging the second capacitor when the source voltage drops. There may further be provide an integrating circuit having a second resistor connected to the voltage detecting circuit and a third capacitor, an output circuit connected to the integration circuit and having a hysteresis characteristic and a third resistor connected between the second capacitor and the second switch circuit. A reset circuit thus structured can dependably output a reset signal at power-on but does not output such a reset signal when the source voltage drops momentarily during a normal operation for a time duration shorter than a specified short length of time.
Inventors
- 👤 Yoshiaki Mitani
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:28
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/22; H03K17/223
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
181 words
A power-on reset circuit which can be incorporated in a semiconductor device for outputting a reset signal for resetting said semiconductor in an initial condition for a specified capacitor-charging period of time when a source voltage is applied, said power-on reset circuit comprising: a first capacitor having a grounded electrode and a source electrode; a second capacitor having a grounded electrode and a source electrode; a first switch circuit connected between the source electrode of said first capacitor and a voltage source; a second switch circuit connecting the source electrodes of said first and second capacitors; a voltage detecting circuit adapted to output a reset-releasing signal when the voltage of said second capacitor reaches a specified threshold voltage; and a discharge circuit comprising a resistor and a diode connected in series for discharging said second capacitor when there is a drop in said source voltage; wherein a momentary drop in said source voltage of less than a specified duration during a normal operation of said semiconductor device does not cause said reset signal to be outputted from said power-on reset circuit.
Claim 2
Dependent Claim
181 words
A power-on reset circuit which can be incorporated in a semiconductor device for outputting a reset signal for resetting said semiconductor in an initial condition for a specified capacitor-charging period of time when a source voltage is applied, said power-on reset circuit comprising: a first capacitor having a grounded electrode and a source electrode; a second capacitor having a grounded electrode and a source electrode; a first switch circuit connected between the source electrode of said first capacitor and a voltage source; a second switch circuit connecting the source electrodes of said first and second capacitors; a voltage detecting circuit adapted to output a reset-releasing signal when the voltage of said second capacitor reaches a specified threshold voltage; and a discharge circuit comprising a resistor and a diode connected in series for discharging said second capacitor when there is a drop in said source voltage; wherein a momentary drop in said source voltage of less than a specified duration during a normal operation of said semiconductor device does not cause said reset signal to be outputted from said power-on reset circuit.
Claim 3
Dependent Claim
40 words
The power-on reset circuit of claim 1 wherein said resistor has resistance of several 10 kΩ to several MΩ, said first capacitor has capacitance of several pF, and said second capacitor has capacitance of several hundred to several thousand pF.
Claim 4
Dependent Claim
16 words
The power-on reset circuit of claim 1 wherein said specified duration is several tens of milliseconds.
Claim 5
Dependent Claim
23 words
The power-on reset circuit of claim 1 wherein said resistor comprises polysilicon and does not cause any parasitic diode to be formed thereby.
Claim 6
Dependent Claim
54 words
The power-on reset circuit of claim 1 further comprising: an integrating circuit including a second resistor connected to said voltage detecting circuit and a third capacitor; an output circuit having a hysteresis characteristic and being connected to said integrating circuit; and a third resistor connected between said second capacitor and said second switch circuit.
Claim 7
Dependent Claim
42 words
The power-on reset circuit of claim 5 wherein said integrating circuit is connected so as to receive output signals from said voltage detecting circuit through said second resistor and said output circuit is adapted to receive signals outputted from said integrating circuit.
Claim 8
Dependent Claim
54 words
The power-on reset circuit of claim 2 further comprising: an integrating circuit including a second resistor connected to said voltage detecting circuit and a third capacitor; an output circuit having a hysteresis characteristic and being connected to said integrating circuit; and a third resistor connected between said second capacitor and said second switch circuit.
Claim 9
Dependent Claim
42 words
The power-on reset circuit of claim 7 wherein said integrating circuit is connected so as to receive output signals from said voltage detecting circuit through said second resistor and said output circuit is adapted to receive signals outputted from said integrating circuit.
Claim 10
Dependent Claim
20 words
The power-on reset circuit of claim 7 wherein said third resistor has resistance of several 10 kΩ to several MΩ.
Claim 11
Dependent Claim
33 words
The power-on reset circuit of claim 1 wherein said voltage-detecting circuit comprises a CMOS inverter circuit adapted to invert output condition thereof when the voltage of said second capacitor reaches said threshold voltage.
Claim 12
Dependent Claim
208 words
A one-chip microcomputer comprising: a central processing unit; memory means for storing data connected to said central processing unit; a power-on reset circuit incorporated on a single chip with said central processing unit and said memory means for outputting a reset signal for resetting said central processing means in an initial condition for a specified capacitor-charging period of time when a source voltage is applied, said power-on reset circuit comprising: a first capacitor having a grounded electrode and a source electrode; a second capacitor having a grounded electrode and a source electrode; a first switch circuit connected between the source electrode of said first capacitor and a voltage source; a second switch circuit connecting the source electrodes of said first and second capacitors; a voltage detecting circuit adapted to output a reset-releasing signal when the voltage of said second capacitor reaches a specified threshold voltage; and a discharge circuit comprising a resistor and a diode connected in series for discharging said second capacitor when there is a drop in said source voltage; wherein a momentary drop in said source voltage of less than a specified duration during a normal operation of said semiconductor device does not cause said reset signal to be outputted from said power-on reset circuit.
Claim 13
Dependent Claim
208 words
A one-chip microcomputer comprising: a central processing unit; memory means for storing data connected to said central processing unit; a power-on reset circuit incorporated on a single chip with said central processing unit and said memory means for outputting a reset signal for resetting said central processing means in an initial condition for a specified capacitor-charging period of time when a source voltage is applied, said power-on reset circuit comprising: a first capacitor having a grounded electrode and a source electrode; a second capacitor having a grounded electrode and a source electrode; a first switch circuit connected between the source electrode of said first capacitor and a voltage source; a second switch circuit connecting the source electrodes of said first and second capacitors; a voltage detecting circuit adapted to output a reset-releasing signal when the voltage of said second capacitor reaches a specified threshold voltage; and a discharge circuit comprising a resistor and a diode connected in series for discharging said second capacitor when there is a drop in said source voltage; wherein a momentary drop in said source voltage of less than a specified duration during a normal operation of said semiconductor device does not cause said reset signal to be outputted from said power-on reset circuit.
Claim 14
Dependent Claim
38 words
The one-chip microcomputer claim 11 wherein said resistor has resistance of several 10 kΩ to several MΩ, said first capacitor has capacitance of several pF, and said second capacitor has capacitance of several hundred to several thousand pF.
Claim 15
Dependent Claim
15 words
The one-chip microcomputer of claim 11 wherein said specified duration is several tens of milliseconds.
Claim 16
Dependent Claim
22 words
The one-chip microcomputer of claim 11 wherein said resistor comprises polysilicon and does not cause any parasitic diode to be formed thereby.
Claim 17
Dependent Claim
53 words
The one-chip microcomputer of claim 11 further comprising: an integrating circuit including a second resistor connected to said voltage detecting circuit and a third capacitor; an output circuit having a hysteresis characteristic and being connected to said integrating circuit; and a third resistor connected between said second capacitor and said second switch circuit.
Claim 18
Dependent Claim
41 words
The one-chip microcomputer of claim 15 wherein said integrating circuit is connected so as to receive output signals from said voltage detecting circuit through said second resistor and said output circuit is adapted to receive signals outputted from said integrating circuit.
Claim 19
Dependent Claim
53 words
The one-chip microcomputer of claim 12 further comprising: an integrating circuit including a second resistor connected to said voltage detecting circuit and a third capacitor; an output circuit having a hysteresis characteristic and being connected to said integrating circuit; and a third resistor connected between said second capacitor and said second switch circuit.
Claim 20
Dependent Claim
41 words
The one-chip microcomputer of claim 17 wherein said integrating circuit is connected so as to receive output signals from said voltage detecting circuit through said second resistor and said output circuit is adapted to receive signals outputted from said integrating circuit.
Claim 21
Dependent Claim
19 words
The one-chip microcomputer of claim 17 wherein said third resistor has resistance of several 10 kΩ to several MΩ.
Claim 22
Dependent Claim
32 words
The one-chip microcomputer of claim 11 wherein said voltage-detecting circuit comprises a CMOS inverter circuit adapted to invert output condition thereof when the voltage of said second capacitor reaches said threshold voltage.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2002-07-26 | 2003-01-25 | 2003-07-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-07-26 | 2007-01-25 | 2007-07-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-07-26 | 2011-01-25 | 2011-07-27 | $7700.00 | Window Closed / Lapsed |