US5923992A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit formed with shallow isolation structures having nitride placed on the trench dielectric
Assignee: Advanced Micro Devices Inc
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Filing: 1997-02-11
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Granted: 1999-07-13
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Expires: 2017-02-11
Abstract
Abstract A method for protecting the trench dielectric fill for a shallow trench isolation structure by forming a protective layer upon the upper surface of the trench dielectric is presented. In a preferred embodiment, the protective layer comprises a layer of nitride formed upon a layer of oxide. Various etch and cleaning processes during the semiconductor device formation may cause damage to the trench dielectric. A shallow trench is typically formed early in the process sequence. A trench dielectric is deposited into the shallow trench and then planarized so that the upper surface of the trench dielectric is at the same level as the upper surface of the trench dielectric. Damage to the upper surface of the trench dielectric may be caused during several of the subsequent processing steps, including: the etch process used to form the polysilicon gate; the etch process used to form oxide spacers upon the sidewall surfaces of the conductive structures; the etch process used to form contact holes through interlevel dielectrics; and the metal deposition into the contact holes used to establish an electrical contact with the conductive structures. By forming a protective nitride layer upon the upper surface of the trench dielectric, the trench dielectric is better protected against damage.
Inventors
- 👤 Thomas E. Spikes
- 👤 Mark I. Gardner
- 👤 Fred N. Hause
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 12:01
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/10; H10W10/01; H10W10/011; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6302; H10P14/6304; H10P14/6314; H10P14/69; H10P14/692; H10P14/6938; H10P14/6939; H10P14/69391
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
134 words
A method for forming an isolation structure, comprising: providing a semiconductor substrate having an upper surface defined by field regions adjacent active regions; removing a portion of the semiconductor substrate upper surface within the field regions to form a trench which serves to electrically isolate adjacent active regions; forming a trench dielectric within said trench such that an upper surface of said trench dielectric is at the same level as an upper surface of said semiconductor substrate; forming a protective layer, subsequent to forming a trench dielectric within said trench, upon said silicon substrate and upon the upper surface of said trench dielectric; removing said protective layer above said active regions while maintaining said protective layer upon the upper surface of said trench dielectric material; and patterning a conductive structure upon said protective layer.
Claim 2
Independent Claim
134 words
A method for forming an isolation structure, comprising: providing a semiconductor substrate having an upper surface defined by field regions adjacent active regions; removing a portion of the semiconductor substrate upper surface within the field regions to form a trench which serves to electrically isolate adjacent active regions; forming a trench dielectric within said trench such that an upper surface of said trench dielectric is at the same level as an upper surface of said semiconductor substrate; forming a protective layer, subsequent to forming a trench dielectric within said trench, upon said silicon substrate and upon the upper surface of said trench dielectric; removing said protective layer above said active regions while maintaining said protective layer upon the upper surface of said trench dielectric material; and patterning a conductive structure upon said protective layer.
Claim 3
Dependent Claim
63 words
The method as recited in claim 1, wherein the step of removing a portion of the semiconductor substrate upper surface comprises: depositing a photoresist layer upon said semiconductor substrate; exposing a portion of said photoresist layer using a mask; removing exposed portion of said photoresist to expose the field regions of said semiconductor substrate; and anisotropically etching the trench into said semiconductor substrate.
Claim 4
Dependent Claim
47 words
The method as recited in claim 1, wherein the step of forming said trench dielectric comprises: depositing a CVD oxide from a TEOS source at a temperature of approximately 400-800° C., and removing the portion of the oxide extending above the upper surface of said semiconductor substrate.
Claim 5
Dependent Claim
48 words
The method as recited in claim 1, wherein the step of forming said protective layer comprises forming a composite layer, wherein said composite layer, comprises: thermally growing an oxide layer upon said silicon substrate and said trench dielectric; and depositing a nitride layer upon said thermally grown oxide.
Claim 6
Dependent Claim
49 words
The method as recited in claim 1, wherein the step of forming said conductive structure comprises: depositing a layer of polysilicon upon said protective layer; patterning the layer of polysilicon to form conductive structures upon a portion of said protective layer in said field regions above said shallow trench.
Claim 7
Dependent Claim
50 words
The method as recited in claim 1, further comprising: forming spacers upon sidewall surfaces of said conductive structures by: depositing a conformal CVD oxide upon said conductive structure and upon said protective layer; and anisotropically etching said oxide to form said spacers upon the sidewall surfaces of said conductive structures.
Claim 8
Independent Claim
162 words
A method for forming an isolation structure, comprising: providing a lightly doped silicon substrate; forming a shallow trench isolation structure into field regions of said silicon substrate, wherein said field regions electrically isolate active regions of said silicon substrate; depositing a CVD trench oxide, from a TEOS source at a temperature of approximately 400-800° C., into said shallow trench isolation structure, wherein an upper surface of said trench oxide is at the same level as an upper surface of said silicon substrate; forming a nitride protective layer, subsequent to depositing a CVD trench oxide into said shallow trench structure, upon the upper surface of said trench oxide and said silicon substrate; removing a portion of said nitride protective layer above said active regions while maintaining a portion of said nitride protective layer upon the upper surface of said trench oxide; forming polysilicon conductive structures upon said protective layer and active regions; and forming oxide spacers upon sidewall surfaces of said conductive structures.
Claim 9
Independent Claim
162 words
A method for forming an isolation structure, comprising: providing a lightly doped silicon substrate; forming a shallow trench isolation structure into field regions of said silicon substrate, wherein said field regions electrically isolate active regions of said silicon substrate; depositing a CVD trench oxide, from a TEOS source at a temperature of approximately 400-800° C., into said shallow trench isolation structure, wherein an upper surface of said trench oxide is at the same level as an upper surface of said silicon substrate; forming a nitride protective layer, subsequent to depositing a CVD trench oxide into said shallow trench structure, upon the upper surface of said trench oxide and said silicon substrate; removing a portion of said nitride protective layer above said active regions while maintaining a portion of said nitride protective layer upon the upper surface of said trench oxide; forming polysilicon conductive structures upon said protective layer and active regions; and forming oxide spacers upon sidewall surfaces of said conductive structures.
Claim 10
Dependent Claim
60 words
The method as recited in claim 7, wherein the step of forming said shallow trench comprises: depositing a photoresist layer upon said silicon substrate; exposing a portion of said photoresist layer using a mask; removing exposed portion of said photoresist to expose the field regions of said silicon substrate; and anisotropically etching a shallow trench void into said silicon substrate.
Claim 11
Dependent Claim
55 words
The method as recited in claim 7, wherein the step of forming said oxide spacers upon said sidewall surfaces of said conductive structures comprises: depositing a CVD oxide upon said conductive structure, said protective layer, and said active regions; anisotropically etching said oxide to form said spacers upon the sidewall surfaces of said conductive structures.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-07-12 | 2003-01-11 | 2003-07-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-07-12 | 2007-01-11 | 2007-07-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-07-12 | 2011-01-11 | 2011-07-13 | $7700.00 | Window Closed / Lapsed |