US5923614A
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US
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Structure and method for reading blocks of data from selectable points in a memory device
Assignee: Xilinx Inc
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Filing: 1998-04-30
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Granted: 1999-07-13
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Expires: 2018-04-30
Abstract
Abstract A self-addressing memory device is provided that can provide blocks of data starting from more than one initial location in the device, and may have the option of reading in either direction. This memory device can efficiently store multiple bitstreams, which may be of different sizes, that are used to configure one or more configurable logic devices. Each stored bitstream can be accessed in any order. In one embodiment, the configurable logic device is a Field Programmable Gate Array ("FPGA"). In one embodiment, the memory device is a Read-Only Memory ("ROM") that is either read up from all zeros or down from all ones. In one embodiment, the ROM includes a bidirectional chip enable chain that permits cascading multiple ROMs.
Inventors
- 👤 Charles R. Erickson
- 👤 Robert O. Conn
- 👤 Lois D. Cartier
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 18:55
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17748; H03K19/17772; G; G11; G11C; G11C8/00; G11C8/04; H03K19/1776
Claims Analysis
Total Claims: 44
Claim 1
Independent Claim
166 words
A method for storing a plurality of bitstreams in a self-addressing memory device, the method comprising the steps of: selecting a first bitstream; selecting a first initial address from a set of initial addresses generated within the memory device; selecting a first direction from two available directions, the two available directions being a direction of increasing addresses and a direction of decreasing addresses; selecting a second bitstream; selecting a second initial address from the set of initial addresses; selecting a second direction from the two available directions; storing the first bitstream in the memory device, beginning at a first location corresponding to the first initial address and storing sequential data in the first direction from the first location until the first bitstream has been completely stored; and storing the second bitstream in the memory device, beginning at a second location corresponding to the second initial address and storing sequential data in the second direction from the second location until the second bitstream has been completely stored.
Claim 2
Independent Claim
166 words
A method for storing a plurality of bitstreams in a self-addressing memory device, the method comprising the steps of: selecting a first bitstream; selecting a first initial address from a set of initial addresses generated within the memory device; selecting a first direction from two available directions, the two available directions being a direction of increasing addresses and a direction of decreasing addresses; selecting a second bitstream; selecting a second initial address from the set of initial addresses; selecting a second direction from the two available directions; storing the first bitstream in the memory device, beginning at a first location corresponding to the first initial address and storing sequential data in the first direction from the first location until the first bitstream has been completely stored; and storing the second bitstream in the memory device, beginning at a second location corresponding to the second initial address and storing sequential data in the second direction from the second location until the second bitstream has been completely stored.
Claim 3
Dependent Claim
57 words
The method of claim 1, wherein: the first initial address is smaller than any other address in the set of initial addresses; the second initial address is larger than any other address in the set of initial addresses; the first direction is the direction of increasing addresses; and the second direction is the direction of decreasing addresses.
Claim 4
Dependent Claim
13 words
The method of claim 1, wherein the first and second directions are different.
Claim 5
Dependent Claim
14 words
The method of claim 1, wherein the first and second directions are the same.
Claim 6
Dependent Claim
15 words
The method of claim 1, wherein the first and second bitstreams are the same size.
Claim 7
Dependent Claim
15 words
The method of claim 1, wherein the first and second bitstreams are of different sizes.
Claim 8
Dependent Claim
13 words
The method of claim 1, wherein the memory device comprises a serial PROM.
Claim 9
Dependent Claim
20 words
The method of claim 1, wherein the memory device comprises a plurality of serial PROMs cascaded in an enable chain.
Claim 10
Dependent Claim
13 words
The method of claim 1, wherein the memory device comprises a parallel PROM.
Claim 11
Dependent Claim
20 words
The method of claim 1, wherein the memory device comprises a plurality of parallel PROMs cascaded in an enable chain.
Claim 12
Dependent Claim
137 words
The method of claim 1, further comprising the steps of: selecting a third bitstream; selecting a third initial address from the set of initial addresses; selecting a third direction from the two available directions; selecting a fourth bitstream; selecting a fourth initial address from the set of initial addresses; selecting a fourth direction from the two available directions; storing the third bitstream in the memory device, beginning at a third location corresponding to the third initial address and storing sequential data in the third direction from the third location until the third bitstream has been completely stored; and storing the fourth bitstream in the memory device, beginning at a fourth location corresponding to the fourth initial address and storing sequential data in the fourth direction from the fourth location until the fourth bitstream has been completely stored.
Claim 13
Dependent Claim
83 words
The method of claim 11, wherein: the first initial address is smaller than any other address in the set of initial addresses; the second initial address is larger than the first initial address; the third initial address is larger than the second initial address; the fourth initial address is larger than any other address in the set of initial addresses; the first and third directions are the direction of increasing addresses; and the second and fourth directions are the direction of decreasing addresses.
Claim 14
Dependent Claim
16 words
The method of claim 12, wherein the second and third initial addresses correspond to adjacent locations.
Claim 15
Independent Claim
162 words
A method for reading a plurality of bitstreams from a self-addressing memory device, the method comprising the steps of: selecting a first initial address from a set of available initial addresses generated within the memory device; selecting a first direction from two available directions, the two available directions being a direction of increasing addresses and a direction of decreasing addresses; reading a first bitstream from the memory device, beginning at a first location corresponding to the first initial address and reading sequential data stored in the first direction from the first location until the first bitstream has been completely read; selecting a second initial address from the set of available initial addresses; selecting a second direction from the two available directions; and reading a second bitstream from the memory device, beginning at a second location corresponding to the second initial address and reading sequential data stored in the second direction from the second location until the second bitstream has been completely read.
Claim 16
Independent Claim
162 words
A method for reading a plurality of bitstreams from a self-addressing memory device, the method comprising the steps of: selecting a first initial address from a set of available initial addresses generated within the memory device; selecting a first direction from two available directions, the two available directions being a direction of increasing addresses and a direction of decreasing addresses; reading a first bitstream from the memory device, beginning at a first location corresponding to the first initial address and reading sequential data stored in the first direction from the first location until the first bitstream has been completely read; selecting a second initial address from the set of available initial addresses; selecting a second direction from the two available directions; and reading a second bitstream from the memory device, beginning at a second location corresponding to the second initial address and reading sequential data stored in the second direction from the second location until the second bitstream has been completely read.
Claim 17
Dependent Claim
57 words
The method of claim 14, wherein: the first initial address is smaller than any other address in the set of initial addresses; the second initial address is larger than any other address in the set of initial addresses; the first direction is the direction of increasing addresses; and the second direction is the direction of decreasing addresses.
Claim 18
Dependent Claim
13 words
The method of claim 14, wherein the first and second directions are different.
Claim 19
Dependent Claim
14 words
The method of claim 14, wherein the first and second directions are the same.
Claim 20
Dependent Claim
15 words
The method of claim 14, wherein the first and second bitstreams are the same size.
Claim 21
Dependent Claim
15 words
The method of claim 14, wherein the first and second bitstreams are of different sizes.
Claim 22
Dependent Claim
17 words
The method of claim 14, wherein the first and second initial addresses are selected using a multiplexer.
Claim 23
Dependent Claim
25 words
The method of claim 14, wherein at least one of the set of initial addresses is stored in a register internal to the memory device.
Claim 24
Dependent Claim
13 words
The method of claim 14, wherein the memory device comprises a serial PROM.
Claim 25
Dependent Claim
20 words
The method of claim 14, wherein the memory device comprises a plurality of serial PROMs cascaded in an enable chain.
Claim 26
Dependent Claim
13 words
The method of claim 14, wherein the memory device comprises a parallel PROM.
Claim 27
Dependent Claim
20 words
The method of claim 14, wherein the memory device comprises a plurality of parallel PROMs cascaded in an enable chain.
Claim 28
Dependent Claim
133 words
The method of claim 14, further comprising the steps of: selecting a third initial address from the set of available initial addresses; selecting a third direction from the two available directions; reading a third bitstream from the memory device, beginning at a third location corresponding to the third initial address and reading sequential data stored in the third direction from the third location until the third bitstream has been completely read; selecting a fourth initial address from the set of available initial addresses; selecting a fourth direction from the two available directions; and reading a fourth bitstream from the memory device, beginning at a fourth location corresponding to the fourth initial address and reading sequential data stored in the fourth direction from the fourth location until the fourth bitstream has been completely read.
Claim 29
Dependent Claim
83 words
The method of claim 26, wherein: the first initial address is smaller than any other address in the set of initial addresses; the second initial address is larger than the first initial address; the third initial address is larger than the second initial address; the fourth initial address is larger than any other address in the set of initial addresses; the first and third directions are the direction of increasing addresses; and the second and fourth directions are the direction of decreasing addresses.
Claim 30
Dependent Claim
16 words
The method of claim 27, wherein the second and third initial addresses correspond to adjacent locations.
Claim 31
Dependent Claim
158 words
A self-addressing memory device having a plurality of stored bitstreams, the memory device comprising: an addressable data space having first and second initial addresses, the data space being readable in either of two directions, the two directions being a direction of increasing addresses and a direction of decreasing addresses; a first bitstream stored in the data space, with a first portion of the first bitstream being stored at a first location corresponding to the first initial address and sequential data of the first bitstream being stored in a first direction from the first location, the first direction being one of the two directions; and a second bitstream stored in the data space, with a first portion of the second bitstream being stored at a second location corresponding to the second initial address and sequential data of the second bitstream being stored in a second direction from the second location, the second direction being one of the two directions.
Claim 32
Dependent Claim
158 words
A self-addressing memory device having a plurality of stored bitstreams, the memory device comprising: an addressable data space having first and second initial addresses, the data space being readable in either of two directions, the two directions being a direction of increasing addresses and a direction of decreasing addresses; a first bitstream stored in the data space, with a first portion of the first bitstream being stored at a first location corresponding to the first initial address and sequential data of the first bitstream being stored in a first direction from the first location, the first direction being one of the two directions; and a second bitstream stored in the data space, with a first portion of the second bitstream being stored at a second location corresponding to the second initial address and sequential data of the second bitstream being stored in a second direction from the second location, the second direction being one of the two directions.
Claim 33
Dependent Claim
50 words
The memory device of claim 29, wherein: the first initial address is the minimum address for the data space; the second initial address is the maximum address for the data space; the first direction is the direction of increasing addresses; and the second direction is the direction of decreasing addresses.
Claim 34
Dependent Claim
14 words
The memory device of claim 29, wherein the first and second directions are different.
Claim 35
Dependent Claim
15 words
The memory device of claim 29, wherein the first and second directions are the same.
Claim 36
Dependent Claim
16 words
The memory device of claim 29, wherein the first and second bitstreams are the same size.
Claim 37
Dependent Claim
16 words
The memory device of claim 29, wherein the first and second bitstreams are of different sizes.
Claim 38
Dependent Claim
14 words
The memory device of claim 29, wherein the memory device comprises a serial PROM.
Claim 39
Dependent Claim
21 words
The memory device of claim 29, wherein the memory device comprises a plurality of serial PROMs cascaded in an enable chain.
Claim 40
Dependent Claim
14 words
The memory device of claim 29, wherein the memory device comprises a parallel PROM.
Claim 41
Dependent Claim
21 words
The memory device of claim 29, wherein the memory device comprises a plurality of parallel PROMs cascaded in an enable chain.
Claim 42
Dependent Claim
131 words
The memory device of claim 29, wherein the data space further has third and fourth initial addresses, the memory device further comprising: a third bitstream stored in the data space, with a first portion of the third bitstream being stored at a third location corresponding to the third initial address and sequential data of the third bitstream being stored in a third direction from the third location, the third direction being one of the two directions; and a fourth bitstream stored in the data space, with a first portion of the fourth bitstream being stored at a fourth location corresponding to the fourth initial address and sequential data of the fourth bitstream being stored in a fourth direction from the fourth location, the fourth direction being one of the two directions.
Claim 43
Dependent Claim
76 words
The memory device of claim 39, wherein: the first initial address is the minimum address for the data space; the second initial address is larger than the first initial address; the third initial address is larger than the second initial address; the fourth initial address is the maximum address for the data space; the first and third directions are the direction of increasing addresses; and the second and fourth directions are the direction of decreasing addresses.
Claim 44
Dependent Claim
17 words
The memory device of claim 40, wherein the second and third initial addresses correspond to adjacent locations.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-07-12 | 2003-01-11 | 2003-07-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-07-12 | 2007-01-11 | 2007-07-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-07-12 | 2011-01-11 | 2011-07-13 | $7700.00 | Window Closed / Lapsed |