CMOS output buffer circuit exhibiting reduced switching noise

Claim 2

A CMOS output buffer circuit comprising: a predriving circuit which receives an input signal and an enable signal, and which generates a first predriving signal and a second predriving signal responsive to the input signal and the enable signal; a sequential driving circuit which receives the first predriving signal and an output signal at an output terminal, and which generates a plurality of first sequential driving signals in order when the output signal is at a first logic level and a plurality of second sequential driving signals in order when the output signal is at a second logic level; and a main driving circuit which receives the first and second predriving signals and the first and second sequential signals, and which generates the output signal as either one of the first logic level and the second logic level responsive to the first and second predriving signals and the first and second sequential driving signals.

Claim 3

The CMOS output buffer circuit according to claim 1, wherein said predriving circuit comprises a logic circuit which is responsive to the input signal and the enable signal to generate a first logic signal and a second logic signal, the first and second logic signals each being at the second logic level when both the input and enable signals are at the first logic level, the first and second logic signals each being at the first logic level when the input signal is at the second logic level and the enable signal is at the first logic level, and the first logic signal being at the first logic level and the second logic signal being at the second logic level when the enable signal is at the second logic level, wherein the first and second logic signals are the first and second predriving signals, respectively.

Claim 4

The CMOS output buffer circuit according to claim 1, wherein said predriving circuit comprises: a logic circuit which is responsive to the input signal and the enable signal to generate a first logic signal and a second logic signal, the first and second logic signals each being at the second logic level when both the input and enable signals are at the first logic level, the first and second logic signals each being at the first logic level when the input signal is at the second logic level and the enable signal is at the first logic level, and the first logic signal being at the first logic level and the second logic signal being at the second logic level when the enable signal is at the second logic level; a first circuit which receives the first logic signal and generates the first predriving signal; and a second circuit which receives the second logic signal and generates the second predriving signal.

Claim 5

The CMOS output buffer circuit according to claim 2, wherein said logic comprises: a NAND gate circuit which receives the input signal and enable signal, and generates the first logic signal; an inverter circuit which receives the enable signal and generates an inverted enable signal; and a NOR gate circuit which receives the inverted enable signal and the enable signal, and generates the second logic signal.

Claim 6

The CMOS output buffer circuit according to claim 3, wherein said logic comprises: a NAND gate circuit which receives the input signal and enable signal, and generates the first logic signal; an inverter circuit which receives the enable signal and generates an inverted enable signal; and a NOR gate circuit which receives the inverted enable signal and the enable signal, and generates the second logic signal.

Claim 7

The CMOS output buffer circuit according to claim 1, wherein said sequential driving circuit comprises: a first delay which receives the first predriving signal and generates a plurality of first delay signals each being delayed relative to a preceding signal by a predetermined time; a second delay which receives the output signal and generates a plurality of second delay signals each being delayed relative to a preceding signal by the predetermined time; a first logic circuit which alternately receives the first and second delay signals, and which generates the first sequential driving signals in order; and a second logic circuit which alternately receives the output signal and the first and second delay signals, and which generates the second sequential driving signals in order.

Claim 8

The CMOS output buffer circuit according to claim 6, wherein said first and second delay circuits are each comprised of a plurality of series connected inverter circuits.

Claim 9

The CMOS output buffer circuit according to claim 7, wherein said first logic circuit comprises a plurality of NAND gate circuits each having one input connected to an output of a corresponding inverter circuit within said first delay circuit and another input connected to an output of a corresponding inverter circuit within said second delay circuit, said respective NAND gate circuits generating a corresponding one of the first sequential driving signals.

Claim 10

The CMOS output buffer circuit according to claim 7, wherein said second logic circuit comprises a plurality of AND gate circuits each having one input connected to an output of a corresponding inverter circuit within said first delay circuit and another input connected to an output of a corresponding inverter circuit within said second delay circuit, said respective AND gate circuits generating a corresponding one of the second sequential driving signals.

Claim 11

The CMOS output buffer circuit according to claim 1, wherein said main driving circuit comprises: a pull-up driver responsive to the first predriving signal and the first sequential driving signals, for making a step-by-step transition of the output signal from a ground potential to a power supply potential; and a pull-down driver responsive to the second predriving signal and the second sequential driving signals, for making a step-by-step transition of the output signal from the power supply potential to the ground potential.

Claim 12

The CMOS output buffer circuit according to claim 10, wherein said pull-up driver comprises a plurality of first conductivity type MOS transistors having current paths connected in parallel between the power supply potential and said output terminal, control terminals of said plurality of first conductivity type MOS transistors respectively receiving the first predriving signal and the first sequential driving signals, and wherein said pull-down driver comprises a plurality of second conductivity type MOS transistors having current paths connected in parallel between said output terminal and the ground potential, control terminals of said plurality of second conductivity type MOS transistors respectively receiving the second predriving signal and the second sequential driving signals.

Claim 13

The CMOS output buffer circuit according to claim 11, wherein said first conductivity type is p-type, and said second conductivity type is n-type.

Claim 14

A CMOS output buffer circuit comprising: a first circuit for receiving an input signal and enable signal and generating a first predriving signal and a second predriving signal; a second circuit for receiving the first predriving signal and an output signal and sequentially generating a plurality of first sequential driving signals at predetermined intervals when the input signal is at a first logic level, and sequentially generating a plurality of second sequential driving signals at the predetermined intervals when the input signal is at a second logic level; and a third circuit for receiving the first and second predriving signals and the first and second sequential driving signals and for generating an output signal at an output terminal, wherein said third circuit includes a plurality of first conductivity type MOS transistors which have current paths connected in parallel between a power supply potential and said output terminal and control terminals respectively receiving the first predriving signals and the first sequential driving signals, and a plurality of second conductivity type MOS transistors which have current paths connected in parallel between said output terminal and a ground potential and control terminals respectively receiving the second predriving and the second sequential driving signals, wherein the output terminal is either gradually charged up to the power supply potential or gradually discharged into the ground potential by the first and second conductivity type MOS transisitors.

Claim 15

A CMOS output buffer circuit comprising: a first circuit for receiving an input signal and enable signal and generating a first predriving signal and a second predriving signal; a second circuit for receiving the first predriving signal and an output signal and sequentially generating a plurality of first sequential driving signals at predetermined intervals when the input signal is at a first logic level, and sequentially generating a plurality of second sequential driving signals at the predetermined intervals when the input signal is at a second logic level; and a third circuit for receiving the first and second predriving signals and the first and second sequential driving signals and for generating an output signal at an output terminal, wherein said third circuit includes a plurality of first conductivity type MOS transistors which have current paths connected in parallel between a power supply potential and said output terminal and control terminals respectively receiving the first predriving signals and the first sequential driving signals, and a plurality of second conductivity type MOS transistors which have current paths connected in parallel between said output terminal and a ground potential and control terminals respectively receiving the second predriving and the second sequential driving signals, wherein the output terminal is either gradually charged up to the power supply potential or gradually discharged into the ground potential by the first and second conductivity type MOS transisitors.

Claim 16

A CMOS output buffer circuit comprising: a predriving circuit which receives an input signal and generates first and second predriving signals; a sequential driving circuit which receives an output signal and at least one of the first and second predriving signals, and which generates a plurality of sequential pull-up driving signals in order when the output signal is at a first logic level and a plurality of sequential pull-down driving signals in order when the output signal is at a second logic level; and a main driving circuit which receives the sequential pull-up and pull-down driving signals and generates an output signal according to the sequential pull-up and pull-down driving signals, wherein the output signal is gradually developed step by step to either one of a first logic level and a second logic level according to the sequential pull-up and pull-down driving signals.

Claim 17

A CMOS output buffer circuit comprising: a predriving circuit which receives an input signal and generates first and second predriving signals; a sequential driving circuit which receives an output signal and at least one of the first and second predriving signals, and which generates a plurality of sequential pull-up driving signals in order when the output signal is at a first logic level and a plurality of sequential pull-down driving signals in order when the output signal is at a second logic level; and a main driving circuit which receives the sequential pull-up and pull-down driving signals and generates an output signal according to the sequential pull-up and pull-down driving signals, wherein the output signal is gradually developed step by step to either one of a first logic level and a second logic level according to the sequential pull-up and pull-down driving signals.

Claim 18

A CMOS output buffer circuit as claimed in claim 14, wherein the first logic level is a power supply potential and the second logic level is a ground potential.

Claim 19

A CMOS output buffer circuit as claimed in claim 14, wherein said main driving circuit includes a plurality of parallel connected pull-up transistors having switching states controlled by the pull-up driving signals and a plurality of parallel connected pull-down transistors having switching states controlled by the pull-down driving signals.

Claim 20

A CMOS output buffer circuit as claimed in claim 15, wherein said main driving circuit includes a plurality of parallel connected pull-up transistors having switching states controlled by the pull-up driving signals and a plurality of parallel connected pull-down transistors having switching states controlled by the pull-down driving signals.