Method of reducing transistor channel length with oxidation inhibiting spacers

Claim 1

A method of fabricating a transistor, comprising the steps of: providing a semiconductor substrate, wherein said semiconductor substrate includes a channel region laterally displaced between a first source/drain region and a second source/drain region; forming first and second dielectric structures on an upper surface of said semiconductor substrate such that said first and second dielectric structures are aligned with said first and second source/drain regions respectively and wherein each said first and second dielectric structure includes a substantially vertical sidewall proximal to said channel region; forming first and second spacer structures on said vertical sidewalls of said first and second dielectric structures respectively, each of said spacer structures including an outer surface and said spacer structures shadowing portions of said channel region proximal to said source/drain regions, wherein forming said first and second spacer structures comprises depositing a dielectric layer on said vertical sidewalls of said first and second dielectric structures respectively; forming a channel dielectric structure laterally displaced between said first and second spacer structures; removing said outer surface of each said spacer structure to expose peripheral portions of said channel region proximal to said source/drain regions; introducing a first concentration of a first impurity into said peripheral portions of said channel region; removing said channel dielectric; forming a gate dielectric over said channel region; forming a conductive gate structure over said gate dielectric; removing said first dielectric structure and said second dielectric structure to expose said source/drain regions; and introducing a second impurity, at a second concentration, into said source/drain regions.

Claim 2

A method of fabricating a transistor, comprising the steps of: providing a semiconductor substrate, wherein said semiconductor substrate includes a channel region laterally displaced between a first source/drain region and a second source/drain region; forming first and second dielectric structures on an upper surface of said semiconductor substrate such that said first and second dielectric structures are aligned with said first and second source/drain regions respectively and wherein each said first and second dielectric structure includes a substantially vertical sidewall proximal to said channel region; forming first and second spacer structures on said vertical sidewalls of said first and second dielectric structures respectively, each of said spacer structures including an outer surface and said spacer structures shadowing portions of said channel region proximal to said source/drain regions, wherein forming said first and second spacer structures comprises depositing a dielectric layer on said vertical sidewalls of said first and second dielectric structures respectively; forming a channel dielectric structure laterally displaced between said first and second spacer structures; removing said outer surface of each said spacer structure to expose peripheral portions of said channel region proximal to said source/drain regions; introducing a first concentration of a first impurity into said peripheral portions of said channel region; removing said channel dielectric; forming a gate dielectric over said channel region; forming a conductive gate structure over said gate dielectric; removing said first dielectric structure and said second dielectric structure to expose said source/drain regions; and introducing a second impurity, at a second concentration, into said source/drain regions.

Claim 16

A method of fabricating a transistor, comprising: providing a semiconductor substrate; forming a dielectric layer on an upper surface of said semiconductor substrate; depositing a photoresist layer on said dielectric layer; patterning said photoresist layer with a photolithography exposure device to expose a region of said dielectric layer, wherein said exposed region of said dielectric layer has a lateral dimension approximately equal to a minimum feature size which can be resolved by said photolithographic exposure device; removing said exposed region of said dielectric layer such that first and second dielectric sidewalls are formed and whereby a channel region of said semiconductor substrate having a lateral dimension approximately equal to said minimum feature size is exposed; forming first and second spacer structures on said first and second dielectric sidewalls respectively such that said first and second spacer structures shadow peripheral portions of said channel region whereby an exposed portion of said channel region has a lateral dimension less than said minimum feature size and wherein each said spacer structure includes an outer surface; forming a channel dielectric structure between said first and second spacer structures; removing said outer surface of said first and second spacer structures to expose said peripheral portions of said exposed region semiconductor substrate; subsequent to said removing said outer surface of said first and second spacer structures, introducing a first concentration of phosphorous into said peripheral portions of said channel region before performing any additional introductions of impurities into said peripheral portions; subsequent to said introducing a first concentration of phosphorous, removing said channel dielectric before performing any additional introductions of impurities into said peripheral portions; forming a gate dielectric on said channel region; forming a conductive gate structure over said gate dielectric; removing said dielectric layer to expose said source/drain regions; and introducing a second concentration of arsenic into said source/drain regions.

Claim 17

A method of fabricating a transistor, comprising: providing a semiconductor substrate; forming a dielectric layer on an upper surface of said semiconductor substrate; depositing a photoresist layer on said dielectric layer; patterning said photoresist layer with a photolithography exposure device to expose a region of said dielectric layer, wherein said exposed region of said dielectric layer has a lateral dimension approximately equal to a minimum feature size which can be resolved by said photolithographic exposure device; removing said exposed region of said dielectric layer such that first and second dielectric sidewalls are formed and whereby a channel region of said semiconductor substrate having a lateral dimension approximately equal to said minimum feature size is exposed; forming first and second spacer structures on said first and second dielectric sidewalls respectively such that said first and second spacer structures shadow peripheral portions of said channel region whereby an exposed portion of said channel region has a lateral dimension less than said minimum feature size and wherein each said spacer structure includes an outer surface; forming a channel dielectric structure between said first and second spacer structures; removing said outer surface of said first and second spacer structures to expose said peripheral portions of said exposed region semiconductor substrate; subsequent to said removing said outer surface of said first and second spacer structures, introducing a first concentration of phosphorous into said peripheral portions of said channel region before performing any additional introductions of impurities into said peripheral portions; subsequent to said introducing a first concentration of phosphorous, removing said channel dielectric before performing any additional introductions of impurities into said peripheral portions; forming a gate dielectric on said channel region; forming a conductive gate structure over said gate dielectric; removing said dielectric layer to expose said source/drain regions; and introducing a second concentration of arsenic into said source/drain regions.

Claim 22

A method of fabricating a transistor, comprising the steps of: providing a semiconductor substrate, wherein said semiconductor substrate includes a channel region laterally displaced between a first source/drain region and a second source/drain region; forming a first and second dielectric structure on an upper surface of said semiconductor substrate such that said first and second dielectric structures are aligned with said first and second source/drain regions respectively and wherein each said first and second dielectric structure includes a substantially vertical sidewall proximal to said channel region; forming first and second spacer structures on said vertical sidewalls of said first and second dielectric structures respectively, each said spacer structure including an outer surface and said spacer structures shadowing portions of said channel region proximal to said source/drain regions, wherein forming said first and second spacer structures comprises depositing a dielectric layer on said vertical sidewalls of said first and second dielectric structures respectively; forming a channel dielectric structure laterally displaced between said first and second spacer structures; removing said outer surface of each said spacer structure to expose peripheral portions of said channel region proximal to said source/drain regions; subsequent to said removing said outer surface of each said spacer structure, introducing a first concentration of a first impurity into said peripheral portions of said channels region before performing any additional introductions of impurities into said peripheral portions; subsequent to said introducing a first concentration of a first impurity, removing said channel dielectric before performing any additional introductions of impurities into said peripheral portions; forming a gate dielectric over said channel region; forming a conductive gate structure over said gate dielectric; removing said first dielectric structure and said second dielectric structure to expose said source/drain regions; and introducing a second impurity, at a second concentration, into said source/drain regions.

Claim 23

A method of fabricating a transistor, comprising the steps of: providing a semiconductor substrate, wherein said semiconductor substrate includes a channel region laterally displaced between a first source/drain region and a second source/drain region; forming a first and second dielectric structure on an upper surface of said semiconductor substrate such that said first and second dielectric structures are aligned with said first and second source/drain regions respectively and wherein each said first and second dielectric structure includes a substantially vertical sidewall proximal to said channel region; forming first and second spacer structures on said vertical sidewalls of said first and second dielectric structures respectively, each said spacer structure including an outer surface and said spacer structures shadowing portions of said channel region proximal to said source/drain regions, wherein forming said first and second spacer structures comprises depositing a dielectric layer on said vertical sidewalls of said first and second dielectric structures respectively; forming a channel dielectric structure laterally displaced between said first and second spacer structures; removing said outer surface of each said spacer structure to expose peripheral portions of said channel region proximal to said source/drain regions; subsequent to said removing said outer surface of each said spacer structure, introducing a first concentration of a first impurity into said peripheral portions of said channels region before performing any additional introductions of impurities into said peripheral portions; subsequent to said introducing a first concentration of a first impurity, removing said channel dielectric before performing any additional introductions of impurities into said peripheral portions; forming a gate dielectric over said channel region; forming a conductive gate structure over said gate dielectric; removing said first dielectric structure and said second dielectric structure to expose said source/drain regions; and introducing a second impurity, at a second concentration, into said source/drain regions.