System for controlling variable length PCI burst data using a dummy final data phase and adjusting the burst length during transaction

Claim 3

Apparatus according to claim 1, wherein each of said data transfer times is defined by a respective clock cycle for which ready signals are asserted by both said source device and said destination device.

Claim 4

A method according to claim 2, wherein said source device asserts a first signal prior to all of said data transfer times and maintains said first signal asserted for all of said data transfer times of said burst, and wherein said step of indicating comprises the step of negating said first signal for said final data transfer time.

Claim 5

A method according to claim 3, wherein said peripheral bus has a data path from said source device to said destination device which is n data units in width, n>0, said peripheral bus further having a respective enable signal corresponding to each of said data units of said data path, wherein said step of performing a burst of at least one data transfer comprises the step of asserting selected ones of said enable signals for each of said data transfer times of said burst, said destination device clocking in data at each particular data transfer time of said burst only from those data units of said data path whose corresponding enable signals are asserted for the particular data transfer time, and wherein said step of inhibiting any data transfer at said final data transfer time comprises the step of negating all of said enable signals for said final data transfer time.

Claim 8

A method according to claim 5, wherein said step of performing a burst of at least one data transfer comprises the step of asserting selected ones of said enable signals for each of said data transfer times of said burst, said destination device clocking in data at each particular data transfer time of said burst only from those data units of said data path whose corresponding enable signals are asserted for the particular data transfer time.

Claim 11

A method according to claim 7, wherein said plurality of data write accesses on said originating bus includes a given data write access in response to which said given data transfer is completed on said peripheral bus, and wherein said failure by said source device to detect pendency at the data transfer time of a given one of said data transfers of said burst, of any next data transfer which is burstable with said given data transfer on said peripheral bus, comprises the steps of: detecting, at the data transfer time of said given data transfer, that no further data transfers are required on said peripheral bus in response to said given data write access on said originating bus; and failing to detect, by the data transfer time of said given data transfer, any next data write access on said originating bus which is burstable with said given data transfer on said peripheral bus.

Claim 12

A method according to claim 7, wherein each data transfer of said burst except said first data transfer has a respective prior data transfer of said burst, and wherein said step of performing a burst of at least one data transfer of said transaction comprises the step of performing each particular data transfer of said burst except said first data transfer of said burst in response to detection by said source device, at the data transfer time of the data transfer prior to the particular data transfer, that said particular data transfer is burstable with the prior data transfer on said peripheral bus.

Claim 15

A method according to claim 10, wherein said bus has a data path from said initiator to said target which is n data units in width, n>0, said bus further having respective enable signals corresponding to each of said data units of said data path, wherein said step of inhibiting any data transfer of said transaction for said final data transfer time, comprises the step of negating all of said enable signals for said final data transfer time.

Claim 16

A method according to claim 11, further comprising the step of asserting at least one of said enable signals for said first data transfer time of said particular transaction.

Claim 19

A method according to claim 13, further comprising the step of asserting at least one of said byte enable signals for said second clock cycle.

Claim 20

A method according to claim 13, further comprising the step of, for a fourth clock cycle of said clock signal, between said second and third clock cycles, asserting said IRDY# signal while maintaining said FRAME# signal asserted.

Claim 21

Apparatus for controlling a burst data write transaction on a peripheral bus, comprising: means for performing a burst of at least one data transfer of said transaction on said peripheral bus from a source device to a destination device, each of said data transfers of said burst occurring at a respective data transfer time; means for establishing a length of said transaction by indicating to said destination device, during said transaction, that a next data transfer time is to be a final data transfer time of said transaction; and means for inhibiting any data transfer on said peripheral bus at said final data transfer time.

Claim 22

Apparatus for controlling a burst data write transaction on a peripheral bus, comprising: means for performing a burst of at least one data transfer of said transaction on said peripheral bus from a source device to a destination device, each of said data transfers of said burst occurring at a respective data transfer time; means for establishing a length of said transaction by indicating to said destination device, during said transaction, that a next data transfer time is to be a final data transfer time of said transaction; and means for inhibiting any data transfer on said peripheral bus at said final data transfer time.

Claim 23

Apparatus according to claim 16, wherein each of said data transfer times is defined by a respective clock cycle for which ready signals are asserted by both said source device and said destination device.

Claim 24

Apparatus according to claim 17, wherein said source device asserts a first signal prior to all of said data transfer times and maintains said first signal asserted for all of said data transfer times of said burst, and wherein said means for indicating comprises circuitry which negates said first signal for said final data transfer time.

Claim 25

Apparatus according to claim 18, wherein said peripheral bus has a data path from said source device to said destination device which is n data units in width, n>0, said peripheral bus further having a respective enable signal corresponding to each of said data units of said data path, wherein said means for performing a burst of at least one data transfer comprises circuitry which asserts selected ones of said enable signals for each of said data transfer times of said burst, said destination device clocking in data at each particular data transfer time of said burst only from those data units of said data path whose corresponding enable signals are asserted for the particular data transfer time, and wherein said means for inhibiting any data transfer at said final data transfer time comprises circuitry which negates all of said enable signals for said final data transfer time.

Claim 26

Apparatus for controlling a burst data write transaction on a peripheral bus having a data path from said source device to said destination device which is n data units in width, n>0, said peripheral bus further having a respective enable signal corresponding to each of said data units of said data path, comprising: means for performing a burst of at least one data transfer of said transaction on said peripheral bus from a source device to a destination device, each of said data transfers of said burst occurring at a respective data transfer time; means for establishing a length of said transaction by indicating to said destination device, during said transaction, that a next data transfer time is to be a final data transfer time of said transaction; and means for inhibiting any data transfer on said peripheral bus at said final data transfer time, wherein said means for inhibiting any data transfer at said final data transfer time comprises circuitry which negates all of said enable signals for said final data transfer time.

Claim 27

Apparatus for controlling a burst data write transaction on a peripheral bus having a data path from said source device to said destination device which is n data units in width, n>0, said peripheral bus further having a respective enable signal corresponding to each of said data units of said data path, comprising: means for performing a burst of at least one data transfer of said transaction on said peripheral bus from a source device to a destination device, each of said data transfers of said burst occurring at a respective data transfer time; means for establishing a length of said transaction by indicating to said destination device, during said transaction, that a next data transfer time is to be a final data transfer time of said transaction; and means for inhibiting any data transfer on said peripheral bus at said final data transfer time, wherein said means for inhibiting any data transfer at said final data transfer time comprises circuitry which negates all of said enable signals for said final data transfer time.

Claim 28

Apparatus according to claim 20, wherein said means for performing a burst of at least one data transfer comprises circuitry which asserts selected ones of said enable signals for each of said data transfer times of said burst, said destination device clocking in data at each particular data transfer time of said burst only from those data units of said data path whose corresponding enable signals are asserted for the particular data transfer time.

Claim 29

Apparatus for controlling a burst data write transaction on a peripheral bus, for use with an originating bus carrying a plurality of data write accesses including a first data write access in response to which said source device begins said burst data write transaction and in response to which a first one of said data transfers of said burst is performed, comprising: means for performing a burst of at least one data transfer of said transaction on said peripheral bus from a source device to a destination device, each of said data transfers of said burst occurring at a respective data transfer time; means for establishing a length of said transaction by indicating to said destination device, during said transaction, that a next data transfer time is to be a final data transfer time of said transaction; and means for inhibiting any data transfer on said peripheral bus at said final data transfer time, wherein said means for indicating that a next data transfer time is to be a final data transfer time, is responsive to failure by said source device to detect pendency at the data transfer time of a given one of said data transfers of said burst, of any next data transfer which is burstable with said given data transfer on said peripheral bus.

Claim 30

Apparatus for controlling a burst data write transaction on a peripheral bus, for use with an originating bus carrying a plurality of data write accesses including a first data write access in response to which said source device begins said burst data write transaction and in response to which a first one of said data transfers of said burst is performed, comprising: means for performing a burst of at least one data transfer of said transaction on said peripheral bus from a source device to a destination device, each of said data transfers of said burst occurring at a respective data transfer time; means for establishing a length of said transaction by indicating to said destination device, during said transaction, that a next data transfer time is to be a final data transfer time of said transaction; and means for inhibiting any data transfer on said peripheral bus at said final data transfer time, wherein said means for indicating that a next data transfer time is to be a final data transfer time, is responsive to failure by said source device to detect pendency at the data transfer time of a given one of said data transfers of said burst, of any next data transfer which is burstable with said given data transfer on said peripheral bus.

Claim 31

Apparatus according to claim 22, wherein said plurality of data write accesses on said originating bus includes a given data write access in response to which said given data transfer is completed on said peripheral bus, and wherein said failure by said source device to detect pendency at the data transfer time of a given one of said data transfers of said burst, of any next data transfer which is burstable with said given data transfer on said peripheral bus, comprises circuitry which: detects, at the data transfer time of said given data transfer, that no further data transfers are required on said peripheral bus in response to said given data write access on said originating bus; and fails to detect, by the data transfer time of said given data transfer, any next data write access on said originating bus which is burstable with said given data transfer on said peripheral bus.

Claim 32

Apparatus according to claim 22, wherein each data transfer of said burst except said first data transfer has a respective prior data transfer of said burst, and wherein said means for performing a burst of at least one data transfer of said transaction comprises circuitry which performs each particular data transfer of said burst except said first data transfer of said burst in response to detection by said source device, at the data transfer time of the data transfer prior to the particular data transfer, that said particular data transfer is burstable with the prior data transfer on said peripheral bus.

Claim 33

Apparatus for controlling a transaction between an initiator and a target on a bus, said bus having a protocol including a burst data write transaction protocol according to which a burst data write transaction begins in response to assertion by said initiator of a first signal, and according to which data transfer times of the transaction are defined by a ready signal from said initiator and a ready signal from said target both being sampled asserted concurrently during the transaction, and according to which said initiator can end the transaction by negating said first signal for a final one of said data transfer times of the transaction, and according to which a data transfer takes place at each of said data transfer times unless inhibited, comprising a synchronous circuit which: asserts said first signal to begin a particular burst data write transaction according to said burst data write transaction protocol; asserts said ready signal from said initiator for a first data transfer time of said particular transaction; and for a final data transfer time of said particular transaction, negates said first signal, asserts said ready signal from said initiator, and inhibits any data transfer of said transaction.

Claim 34

Apparatus for controlling a transaction between an initiator and a target on a bus, said bus having a protocol including a burst data write transaction protocol according to which a burst data write transaction begins in response to assertion by said initiator of a first signal, and according to which data transfer times of the transaction are defined by a ready signal from said initiator and a ready signal from said target both being sampled asserted concurrently during the transaction, and according to which said initiator can end the transaction by negating said first signal for a final one of said data transfer times of the transaction, and according to which a data transfer takes place at each of said data transfer times unless inhibited, comprising a synchronous circuit which: asserts said first signal to begin a particular burst data write transaction according to said burst data write transaction protocol; asserts said ready signal from said initiator for a first data transfer time of said particular transaction; and for a final data transfer time of said particular transaction, negates said first signal, asserts said ready signal from said initiator, and inhibits any data transfer of said transaction.

Claim 35

Apparatus according to claim 25, wherein said bus has a data path from said initiator to said target which is n data units in width, n>0, said bus further having respective enable signals corresponding to each of said data units of said data path, wherein said circuit inhibits any data transfer of said transaction for said final data transfer time, by negating all of said enable signals for said final data transfer time.

Claim 36

Apparatus according to claim 26, wherein said circuit further asserts at least one of said enable signals for said first data transfer time of said particular transaction.

Claim 37

Apparatus for controlling a PCI-bus, for use with a PCI-bus clock signal, comprising a synchronous circuit having: a first state in which said circuit asserts a PCI-bus FRAME# signal; a second state occurring after said first state, in which said circuit asserts a PCI-bus IRDY# signal while maintaining said FRAME# signal asserted; and a third state occurring after said second state, in which said circuit negates said FRAME# signal with said IRDY# signal asserted and all byte enable signals of said PCI-bus negated.

Claim 38

Apparatus for controlling a PCI-bus, for use with a PCI-bus clock signal, comprising a synchronous circuit having: a first state in which said circuit asserts a PCI-bus FRAME# signal; a second state occurring after said first state, in which said circuit asserts a PCI-bus IRDY# signal while maintaining said FRAME# signal asserted; and a third state occurring after said second state, in which said circuit negates said FRAME# signal with said IRDY# signal asserted and all byte enable signals of said PCI-bus negated.

Claim 39

Apparatus according to claim 28, wherein in said second state, said circuit further asserts at least one of said byte enable signals.

Claim 40

Apparatus according to claim 28, wherein said circuit further comprises a fourth state, occurring between said second and third states, in which said circuit asserts said IRDY# signal while maintaining said FRAME# signal asserted.