Patent US5915083A successfully refreshed from Google Patents.
US5915083A
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US
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Smart debug interface circuit for efficiently for debugging a software application for a programmable digital processor device
Assignee: NXP BV
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Filing: 1997-02-28
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Granted: 1999-06-22
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Expires: 2017-02-28
Abstract
Abstract The present invention comprises a smart debug interface circuit for the diagnostic testing and debugging of a software application for a programmable digital processor system. The smart debug interface circuit of the present invention includes an instruction register for coupling to an instruction bus of a programmable digital processor. The instruction register is adapted to drive instructions onto the instruction bus. The instruction register couples to the instruction bus in a parallel manner. The smart debug interface circuit of the present invention includes a data register for coupling to a data bus of the programmable digital processor. The data register is adapted to read data from the data bus and couples to the data bus in a parallel manner. The instruction register and data register are each coupled to an interface port. The interface port couples the smart debug interface circuit to a host computer system. A control logic circuit is also included in the smart debug interface circuit of the present invention. The control logic circuit is coupled to the instruction register, the data register, and the interface port. The control logic circuit interfaces a debugging program on the host computer system to the programmable digital processor. Additionally, the control logic circuit interfaces the debugging program with the programmable digital processor without imposing boundary scan bus delay on the instruction bus or the data bus.
Inventors
- 👤 Christian Ponte
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 23:25
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/362; G06F11/3648; G06F11/3656; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/31705; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318583; G06F11/22; G06F11/26; G06F11/261
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
190 words
A smart debug interface circuit for debugging a software application for a programmable digital processor device, comprising: an instruction register coupling to an instruction bus of a programmable digital processor, said instruction register adapted to drive said instruction bus, said instruction register coupled in parallel to said instruction bus such that said instruction bus is not broken by said instruction register; a data register for coupling to a data bus of said programmable digital processor, said data register adapted to read from said data bus, said data register coupled in parallel to said data bus; an interface port for coupling to a host computer system, said interface port coupled to said instruction register and said data register; and a control logic circuit for coupling to a programmable digital processor, said control logic circuit coupled to said data register, said instruction register, and said interface port, said control logic circuit adapted to interface with said host computer system such that a debugging program on said host computer system interfaces with software executing on said programmable digital processor without imposing boundary scan bus delay on said instruction bus or said data bus.
Claim 2
Dependent Claim
190 words
A smart debug interface circuit for debugging a software application for a programmable digital processor device, comprising: an instruction register coupling to an instruction bus of a programmable digital processor, said instruction register adapted to drive said instruction bus, said instruction register coupled in parallel to said instruction bus such that said instruction bus is not broken by said instruction register; a data register for coupling to a data bus of said programmable digital processor, said data register adapted to read from said data bus, said data register coupled in parallel to said data bus; an interface port for coupling to a host computer system, said interface port coupled to said instruction register and said data register; and a control logic circuit for coupling to a programmable digital processor, said control logic circuit coupled to said data register, said instruction register, and said interface port, said control logic circuit adapted to interface with said host computer system such that a debugging program on said host computer system interfaces with software executing on said programmable digital processor without imposing boundary scan bus delay on said instruction bus or said data bus.
Claim 3
Dependent Claim
27 words
The smart debug interface circuit of claim 1 wherein said smart debug interface circuit is adapted to comply with Institute of Electrical and Electronics Engineers standard 1149.1.
Claim 4
Dependent Claim
32 words
The smart debug interface circuit of claim 1 wherein said data register is coupled in parallel to said data bus such that said data bus is not broken by said data register.
Claim 5
Dependent Claim
21 words
The smart debug interface circuit of claim 1 wherein said instruction register is adapted drive an instruction onto said instruction bus.
Claim 6
Dependent Claim
20 words
The smart debug interface circuit of claim 1 wherein said data register adapted to read data from said data bus.
Claim 7
Dependent Claim
50 words
The smart debug interface circuit of claim 1 wherein said control logic circuit is adapted to assert an interrupt to said programmable digital processor to stop an application program running on said programmable digital processor for debugging and assert an interrupt return instruction to restart said application program after debugging.
Claim 8
Dependent Claim
36 words
The smart debug interface circuit of claim 1 wherein said control logic circuit is adapted to automatically send a no operation instruction to said programmable digital processor if said programmable digital processor has a multistage pipeline.
Claim 9
Dependent Claim
42 words
The smart debug interface circuit of claim 1 wherein said control logic circuit is adapted to tristate a memory coupled to said instruction bus so that said instruction register can transmit an instruction to said programmable digital processor via said instruction bus.
Claim 10
Dependent Claim
47 words
The smart debug interface circuit of claim 8 wherein said control logic circuit is adapted to interface with said programmable digital processor such that said programmable digital processor properly executes when said instruction is a two word instruction and said programmable digital processor includes a multistage pipeline.
Claim 11
Independent Claim
202 words
A system for debugging a programmable digital processor device, comprising: an instruction register coupled to an instruction bus of a programmable digital processor, said instruction register coupled in parallel to said instruction bus such that said instruction bus is not broken by said instruction register; a data register for coupling to a data bus of said programmable digital processor, said data register coupled in parallel to said data bus such that said data bus is not broken by said data register; an interface port for coupling to a host computer system, said interface port coupled to said instruction register and said data register; and a host computer system coupled to said interface port for running a debugging program, said debugging program for interfacing with said programmable digital processor and debugging a software application running on said programmable digital processor; and a control logic circuit for coupling to a programmable digital processor, said control logic circuit coupled to said data register, said instruction register, and said interface port, said control logic circuit adapted to interface said debugging program to said programmable digital processor without imposing boundary scan bus delay on said instruction bus or said data bus and slowing said programmable digital processor.
Claim 12
Independent Claim
202 words
A system for debugging a programmable digital processor device, comprising: an instruction register coupled to an instruction bus of a programmable digital processor, said instruction register coupled in parallel to said instruction bus such that said instruction bus is not broken by said instruction register; a data register for coupling to a data bus of said programmable digital processor, said data register coupled in parallel to said data bus such that said data bus is not broken by said data register; an interface port for coupling to a host computer system, said interface port coupled to said instruction register and said data register; and a host computer system coupled to said interface port for running a debugging program, said debugging program for interfacing with said programmable digital processor and debugging a software application running on said programmable digital processor; and a control logic circuit for coupling to a programmable digital processor, said control logic circuit coupled to said data register, said instruction register, and said interface port, said control logic circuit adapted to interface said debugging program to said programmable digital processor without imposing boundary scan bus delay on said instruction bus or said data bus and slowing said programmable digital processor.
Claim 13
Dependent Claim
44 words
The system of claim 10 wherein said control logic circuit is adapted to interface with said programmable digital processor such that said programmable digital processor properly executes when said instruction is a two word instruction and said programmable digital processor includes a multistage pipeline.
Claim 14
Dependent Claim
18 words
The system of claim 11 wherein said instruction register is adapted drive an instruction onto said instruction bus.
Claim 15
Dependent Claim
18 words
The system of claim 11 wherein said data register is adapted to read data from said data bus.
Claim 16
Dependent Claim
47 words
The system of claim 11 wherein said control logic circuit is adapted to assert an interrupt to said programmable digital processor to stop an application program running on said programmable digital processor for debugging and assert an interrupt return instruction to restart said application program after debugging.
Claim 17
Dependent Claim
46 words
The system of claim 11 wherein said control logic circuit is adapted to automatically send a no operation instruction to said programmable digital processor, if said programmable digital processor has a multistage pipeline, such that said programmable digital processor can execute one instruction at a time.
Claim 18
Dependent Claim
23 words
The system of claim 11 wherein said interface port is adapted to comply with Institute of Electrical and Electronics Engineers (IEEE) standard 1149.1.
Claim 19
Dependent Claim
39 words
The system of claim 11 wherein said control logic circuit is adapted to tristate a memory coupled to said instruction bus so that said instruction register can transmit an instruction to said programmable digital processor via said instruction bus.
References Cited (Backward Citations)
US4924382A
Cited
US5053949A
Cited
US5479652A
Cited
US5488728A
Cited
US5479652B1
Cited
US5530804A
Cited
US5544311A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-06-21 | 2002-12-21 | 2003-06-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-06-21 | 2006-12-21 | 2007-06-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-06-21 | 2010-12-21 | 2011-06-22 | $7700.00 | Window Closed / Lapsed |