Method of fabricating a capacitor structure for a dynamic random access memory

Claim 1

A method of fabricating a capacitor structure for a dynamic random access memory, comprising the steps of: providing a transistor on a semiconductor substrate, wherein the transistor includes source/drain regions and a gate electrode having sidewalls thereon, and spacers cover the sidewalls of the gate electrode; forming a first oxide layer over the transistor, the first oxide layer having a first contact opening exposing the source region of the transistor; depositing a bit line into the contact opening and make contacting with the source region of the transistor; forming a second oxide layer over the bit line and the first oxide layer; forming a silicon nitride layer over the second oxide layer; forming a third oxide layer over the silicon nitride layer; patterning the third oxide layer and the silicon nitride layer to form an opening exposing the second oxide layer; using a photoresist mask to expose the portions of the third oxide layer; etch removing the portions of the third oxide layer until the silicon nitride is exposed, and further removing the second oxide layer and the exposed first oxide layer to form a second contact opening exposing the drain region of the transistor; removing the photoresist mask; depositing a hemispherical grained silicon layer over the third oxide layer, the silicon nitride layer and the sildewalls of the second contact opening, and make contacting with the drain region exposed by the second contact opening; forming a polysilicon layer over the hemispherical grained silicon layer and into the second contact opening; removing the polysilicon layer and the hemispherical grained silicon layer over the third oxide layer until the third oxide layer is exposed to form a bottom electrode; further removing the third oxide layer exposed until the silicon nitride is exposed; forming a dielectric layer over the bottom electrode; and forming a top electrode over the dielectric electrode.

Claim 2

A method of fabricating a capacitor structure for a dynamic random access memory, comprising the steps of: providing a transistor on a semiconductor substrate, wherein the transistor includes source/drain regions and a gate electrode having sidewalls thereon, and spacers cover the sidewalls of the gate electrode; forming a first oxide layer over the transistor, the first oxide layer having a first contact opening exposing the source region of the transistor; depositing a bit line into the contact opening and make contacting with the source region of the transistor; forming a second oxide layer over the bit line and the first oxide layer; forming a silicon nitride layer over the second oxide layer; forming a third oxide layer over the silicon nitride layer; patterning the third oxide layer and the silicon nitride layer to form an opening exposing the second oxide layer; using a photoresist mask to expose the portions of the third oxide layer; etch removing the portions of the third oxide layer until the silicon nitride is exposed, and further removing the second oxide layer and the exposed first oxide layer to form a second contact opening exposing the drain region of the transistor; removing the photoresist mask; depositing a hemispherical grained silicon layer over the third oxide layer, the silicon nitride layer and the sildewalls of the second contact opening, and make contacting with the drain region exposed by the second contact opening; forming a polysilicon layer over the hemispherical grained silicon layer and into the second contact opening; removing the polysilicon layer and the hemispherical grained silicon layer over the third oxide layer until the third oxide layer is exposed to form a bottom electrode; further removing the third oxide layer exposed until the silicon nitride is exposed; forming a dielectric layer over the bottom electrode; and forming a top electrode over the dielectric electrode.