Method for fabricating cylindrical capacitor for a memory cell

Claim 1

A method of fabrication of a capacitor having a hemispherical grain layer over the inner surface of a cylindrical electrode, comprising the steps of: a) forming first insulating layer over a substrate; b) chemical-mechanical polishing said first insulating layer for global planarization; c) forming a first barrier layer composed of silicon nitride over said first insulating layer; d) forming a contact opening through said first insulating layer and said first barrier layer exposing said substrate; e) filling said contact opening and covering said first barrier layer with a conductive material; f) removing said conductive material over said first barrier layer forming a plug in said contact opening; the removal of said conductive material performed using a chemical-mechanical polishing process; g) forming a second insulating layer composed of an oxide over said first barrier layer; said second insulating layer having a top surface; h) forming a first opening and a second opening in said second insulating layer, said first opening having a larger open dimension than said second opening; said second opening exposing said plug; i) forming a polysilicon layer on said top surface of said second insulating layer, on said second insulating layer in said first and second openings, and over said plug; said polysilicon layer composed of insitu doped polysilicon; j) forming a hemispherical grain film over said polysilicon layer; k) removing said polysilicon layer and said hemispherical grain film over said top surface of said second insulating layer; said removal of said polysilicon layer performed with a chemical-mechanical polishing process; l) selectively etching and removing said second insulating layer thereby forming a cylindrical top; a cylindrical bottom electrode is comprised of said cylindrical top and said plug; m) forming a capacitor dielectric layer over said cylindrical top; and n) forming a top electrode over said capacitor dielectric layer.

Claim 2

A method of fabrication of a capacitor having a hemispherical grain layer over the inner surface of a cylindrical electrode, comprising the steps of: a) forming first insulating layer over a substrate; b) chemical-mechanical polishing said first insulating layer for global planarization; c) forming a first barrier layer composed of silicon nitride over said first insulating layer; d) forming a contact opening through said first insulating layer and said first barrier layer exposing said substrate; e) filling said contact opening and covering said first barrier layer with a conductive material; f) removing said conductive material over said first barrier layer forming a plug in said contact opening; the removal of said conductive material performed using a chemical-mechanical polishing process; g) forming a second insulating layer composed of an oxide over said first barrier layer; said second insulating layer having a top surface; h) forming a first opening and a second opening in said second insulating layer, said first opening having a larger open dimension than said second opening; said second opening exposing said plug; i) forming a polysilicon layer on said top surface of said second insulating layer, on said second insulating layer in said first and second openings, and over said plug; said polysilicon layer composed of insitu doped polysilicon; j) forming a hemispherical grain film over said polysilicon layer; k) removing said polysilicon layer and said hemispherical grain film over said top surface of said second insulating layer; said removal of said polysilicon layer performed with a chemical-mechanical polishing process; l) selectively etching and removing said second insulating layer thereby forming a cylindrical top; a cylindrical bottom electrode is comprised of said cylindrical top and said plug; m) forming a capacitor dielectric layer over said cylindrical top; and n) forming a top electrode over said capacitor dielectric layer.

Claim 7

A method of fabrication of a capacitor having an hemispherical grain film over the both the inner and outer surfaces of a cylindrical electrode, comprising the steps of: a) forming first insulating layer over said substrate; b) chemical-mechanical polishing said first insulating layer for global planarization; c) forming a first barrier layer composed of silicon nitride over said first insulating layer; d) forming a contact opening through said first insulating layer and said first barrier layer exposing said substrate; e) filling said contact opening and covering said first barrier layer with a conductive material comprising insitu doped polysilicon; f) removing said conductive material over said first barrier layer forming a plug in said contact opening; the removal of said conductive material performed using a chemical-mechanical polishing process; g) forming a second insulating layer composed of an oxide over said first barrier layer; said second insulating layer having a top surface; h) forming a first opening and a second opening in said second insulating layer, said first opening having a larger open dimension than said second opening; said second opening exposing said plug; i) forming a polysilicon layer on said top surface of said second insulating layer, on said second insulating layer in said first opening and said second opening, and over said plug; said polysilicon layer composed of insitu doped polysilicon; j) chemical-mechanical polishing and removing said polysilicon layer on said top surface of said second insulating layer; k) selectively etching and removing said second insulating layer thereby forming a cylindrical top; a cylindrical bottom electrode is comprised of said cylindrical top and said plug; l) depositing a hemispherical grain layer over said cylindrical top and over said first barrier layer; m) reactive ion etching said hemispherical grain layer removing said hemispherical grain layer over said first barrier layer; n) forming a capacitor dielectric layer over said cylindrical top; o) forming a top electrode at least over said capacitor dielectric layer.

Claim 8

A method of fabrication of a capacitor having an hemispherical grain film over the both the inner and outer surfaces of a cylindrical electrode, comprising the steps of: a) forming first insulating layer over said substrate; b) chemical-mechanical polishing said first insulating layer for global planarization; c) forming a first barrier layer composed of silicon nitride over said first insulating layer; d) forming a contact opening through said first insulating layer and said first barrier layer exposing said substrate; e) filling said contact opening and covering said first barrier layer with a conductive material comprising insitu doped polysilicon; f) removing said conductive material over said first barrier layer forming a plug in said contact opening; the removal of said conductive material performed using a chemical-mechanical polishing process; g) forming a second insulating layer composed of an oxide over said first barrier layer; said second insulating layer having a top surface; h) forming a first opening and a second opening in said second insulating layer, said first opening having a larger open dimension than said second opening; said second opening exposing said plug; i) forming a polysilicon layer on said top surface of said second insulating layer, on said second insulating layer in said first opening and said second opening, and over said plug; said polysilicon layer composed of insitu doped polysilicon; j) chemical-mechanical polishing and removing said polysilicon layer on said top surface of said second insulating layer; k) selectively etching and removing said second insulating layer thereby forming a cylindrical top; a cylindrical bottom electrode is comprised of said cylindrical top and said plug; l) depositing a hemispherical grain layer over said cylindrical top and over said first barrier layer; m) reactive ion etching said hemispherical grain layer removing said hemispherical grain layer over said first barrier layer; n) forming a capacitor dielectric layer over said cylindrical top; o) forming a top electrode at least over said capacitor dielectric layer.

Claim 12

A method of fabrication of a capacitor having an hemispherical grain layer over the inner surface of a cylindrical electrode, comprising the steps of: a) forming first insulating layer over a substrate; b) chemical-mechanical polishing said first insulating layer for global planarization; c) forming a first barrier layer composed of silicon nitride over said first insulating layer; d) forming a contact opening through said first insulating layer and said first barrier layer exposing said substrate; e) filling said contact opening and covering said first barrier layer with a conductive material comprising insitu doped polysilicon; f) removing said conductive material over said first barrier layer forming a plug in said contact opening; the removal of said conductive material performed using a process chemical-mechanical polishing process; g) forming a second insulating layer composed of an oxide over said first barrier layer; said second insulating layer having a top surface; h) forming a first opening and a second opening in said second insulating layer, said first opening having a larger open dimension than said second opening; said second opening exposing said plug; forming said first and second openings using a one photoresist layer with three thickness levels by: i) forming a photoresist layer having a zero thickness area, an intermediate thickness area and a full thickness area; said photoresist layer formed by a process selected from the group consisting of e-beam exposure and half-tone optical mask exposure; j) in a first etch step, selectively etching said second insulating layer in said zero thickness area where said photoresist layer is substantially removed to form said second opening in said second insulating layer; k) in a second etch step, selectively etching to remove said intermediate thickness area of said photoresist layer; l) in a third etch step, selectively etching said second insulating layer in said zero thickness area and said intermediate thickness area where said photoresist layer is substantially removed to form a first opening partially through said second insulating layer; m) forming a polysilicon layer over said top surface of said second insulating layer, on said second insulating layer defining said first and second openings, and over said plug; said polysilicon layer composed of insitu doped polysilicon; n) forming a hemispherical grain film over said polysilicon layer; o) removing said polysilicon layer over said top surface of said second insulating layer; said removal of said polysilicon layer performed with a chemical-mechanical polishing process; p) selectively etching and removing said second insulating layer thereby forming a cylindrical top; a cylindrical bottom electrode is comprised of said cylindrical top and said plug; q) forming a capacitor dielectric layer over said cylindrical top; and r) forming a top electrode over said capacitor dielectric layer.

Claim 13

A method of fabrication of a capacitor having an hemispherical grain layer over the inner surface of a cylindrical electrode, comprising the steps of: a) forming first insulating layer over a substrate; b) chemical-mechanical polishing said first insulating layer for global planarization; c) forming a first barrier layer composed of silicon nitride over said first insulating layer; d) forming a contact opening through said first insulating layer and said first barrier layer exposing said substrate; e) filling said contact opening and covering said first barrier layer with a conductive material comprising insitu doped polysilicon; f) removing said conductive material over said first barrier layer forming a plug in said contact opening; the removal of said conductive material performed using a process chemical-mechanical polishing process; g) forming a second insulating layer composed of an oxide over said first barrier layer; said second insulating layer having a top surface; h) forming a first opening and a second opening in said second insulating layer, said first opening having a larger open dimension than said second opening; said second opening exposing said plug; forming said first and second openings using a one photoresist layer with three thickness levels by: i) forming a photoresist layer having a zero thickness area, an intermediate thickness area and a full thickness area; said photoresist layer formed by a process selected from the group consisting of e-beam exposure and half-tone optical mask exposure; j) in a first etch step, selectively etching said second insulating layer in said zero thickness area where said photoresist layer is substantially removed to form said second opening in said second insulating layer; k) in a second etch step, selectively etching to remove said intermediate thickness area of said photoresist layer; l) in a third etch step, selectively etching said second insulating layer in said zero thickness area and said intermediate thickness area where said photoresist layer is substantially removed to form a first opening partially through said second insulating layer; m) forming a polysilicon layer over said top surface of said second insulating layer, on said second insulating layer defining said first and second openings, and over said plug; said polysilicon layer composed of insitu doped polysilicon; n) forming a hemispherical grain film over said polysilicon layer; o) removing said polysilicon layer over said top surface of said second insulating layer; said removal of said polysilicon layer performed with a chemical-mechanical polishing process; p) selectively etching and removing said second insulating layer thereby forming a cylindrical top; a cylindrical bottom electrode is comprised of said cylindrical top and said plug; q) forming a capacitor dielectric layer over said cylindrical top; and r) forming a top electrode over said capacitor dielectric layer.