Dram comprising stacked-type capacitor having vertically protruding part and method of manufacturing the same

Claim 2

A storage element for a DRAM, comprising: a semiconductor substrate of a first conductivity-type including an impurity region of a second conductivity-type formed therein; an insulating layer formed on a main surface of said semiconductor substrate and having an opening which reaches said impurity region; and a capacitor comprising a seamless lower electrode layer including a first part formed along the surface of said insulating layer to be connected through said opening to said impurity region and a second part formed integrally protruding upward from the surface of said first part and having an upper planar surface parallel to said substrate, a dielectric layer formed on the surface of said lower electrode layer, and an upper electrode layer of the capacitor formed on the surface of said dielectric layer.

Claim 3

A storage element for a DRAM, comprising: a semiconductor substrate of a first conductivity-type including an impurity region of a second conductivity-type formed therein; an insulating layer formed on a main surface of said semiconductor substrate and having an opening which reaches said impurity region; a capacitor comprising a lower electrode layer including a first part formed along the surface of said insulating layer to be connected through said opening to said impurity region and a second part formed integrally protruding upward from the surface of said first part and having an upper planar surface parallel to said substrate, at least one of the inner and outer sidewall surfaces of said second part having a stepped region characterized by vertical and horizontal adjoining portions, said second part surrounding a space whose section taken along a line perpendicular to the main surface of said semiconductor substrate having an axially symmetrical configuration, a dielectric layer formed on the surface of said lower electrode layer, and an upper electrode layer of the capacitor formed on the surface of said dielectric layer.

Claim 4

A storage element for a DRAM, comprising: a semiconductor substrate of a first conductivity-type including an impurity region of a second conductivity-type formed therein; an insulating layer formed on a main surface of said semiconductor substrate and having an opening which reaches said impurity region; a capacitor comprising a lower electrode layer including a first part formed along the surface of said insulating layer to be connected through said opening to said impurity region and a second part formed integrally protruding upward from the surface of said first part and having an upper planar surface parallel to said substrate, at least one of the inner and outer sidewall surfaces of said second part having a stepped region characterized by vertical and horizontal adjoining portions, said second part surrounding a space whose section taken along a line perpendicular to the main surface of said semiconductor substrate having an axially symmetrical configuration, a dielectric layer formed on the surface of said lower electrode layer, and an upper electrode layer of the capacitor formed on the surface of said dielectric layer.

Claim 5

A storage element for a DRAM, comprising: a semiconductor substrate of a first conductivity-type having a main surface and including an impurity region of a second conductivity-type formed therein; an insulating layer formed on the main surface of said semiconductor substrate and having an opening which reaches said impurity region; a capacitor comprising (a) a seamless lower electrode layer including a first part formed along the surface of said insulating layer to be connected through said opening to said impurity region and a second part protruding upward from the surface of said first part to surround side surfaces of a space whose section taken along a line perpendicular to the main surface of said semiconductor substrate has an axially symmetrical configuration, (b) a dielectric layer formed on the surface of said lower electrode layer, and (c) an upper electrode layer formed on the surface of said dielectric layer.

Claim 6

A storage element for a DRAM, comprising: a semiconductor substrate of a first conductivity-type having a main surface and including an impurity region of a second conductivity-type formed therein; an insulating layer formed on the main surface of said semiconductor substrate and having an opening which reaches said impurity region; a capacitor comprising (a) a seamless lower electrode layer including a first part formed along the surface of said insulating layer to be connected through said opening to said impurity region and a second part protruding upward from the surface of said first part to surround side surfaces of a space whose section taken along a line perpendicular to the main surface of said semiconductor substrate has an axially symmetrical configuration, (b) a dielectric layer formed on the surface of said lower electrode layer, and (c) an upper electrode layer formed on the surface of said dielectric layer.

Claim 7

A charge storage element for a DRAM connected to impurity regions formed on a main surface of a semiconductor substrate having impurity regions formed therein, comprising: (A) a first conductive layer made by (a) forming a first insulating layer on the main surface of said semiconductor substrate with an opening which reaches said impurity regions; (b) forming a first conductive layer on the surface of said first insulating layer and inside said opening; (c) forming an opening region on the periphery of a region of said first conductive layer to be a lower electrode of one stacked capacitor to reach said first insulating layer; (d) forming a second insulating layer in said opening region; (e) etching said first conductive layer so that the upper part of said second insulating layer protrudes from the surface of said first conductive layer; (f) forming a sidewall insulating layer on the side surface of said second insulating layer protruding from the surface of said first conductive layer; (g) etching said first conductive layer using said sidewall insulating layer as a mask to form a concave part in the inner part of said first conductive layer; and (h) removing said second insulating layer and said sidewall insulating layer; (B) a dielectric layer on the surface of said first conductive layer; and (C) a second conductive layer on the surface of said dielectric layer.

Claim 8

A charge storage element for a DRAM connected to impurity regions formed on a main surface of a semiconductor substrate having impurity regions formed therein, comprising: (A) a first conductive layer made by (a) forming a first insulating layer on the main surface of said semiconductor substrate with an opening which reaches said impurity regions; (b) forming a first conductive layer on the surface of said first insulating layer and inside said opening; (c) forming an opening region on the periphery of a region of said first conductive layer to be a lower electrode of one stacked capacitor to reach said first insulating layer; (d) forming a second insulating layer in said opening region; (e) etching said first conductive layer so that the upper part of said second insulating layer protrudes from the surface of said first conductive layer; (f) forming a sidewall insulating layer on the side surface of said second insulating layer protruding from the surface of said first conductive layer; (g) etching said first conductive layer using said sidewall insulating layer as a mask to form a concave part in the inner part of said first conductive layer; and (h) removing said second insulating layer and said sidewall insulating layer; (B) a dielectric layer on the surface of said first conductive layer; and (C) a second conductive layer on the surface of said dielectric layer.

Claim 9

A charge storage element for a DRAM connected to impurity regions formed on a main surface of a semiconductor substrate having impurity regions formed therein, comprising: (A) a first conductive layer made by (a) forming a first insulating layer on a main surface of a semiconductor substrate including impurity regions formed therein to have an opening which reaches said impurity region; (b) forming a first conductive layer on the surface of said first insulating layer and inside said opening; (c) forming an opening region which reaches said first insulating layer on the periphery of a region of said first conductive layer to be a lower electrode of one stacked capacitor; (d) selectively forming a mask layer for etching on the surface of said first conductive layer surrounded by said opening region; and (e) etching said first conductive layer using said mask layer for etching as a mask to form a concave part in the surface of said first conductive layer; (B) a dielectric layer on the surface of said first conductive layer; and (C) a second conductive layer on the surface of said dielectric layer.

Claim 10

A charge storage element for a DRAM connected to impurity regions formed on a main surface of a semiconductor substrate having impurity regions formed therein, comprising: (A) a first conductive layer made by (a) forming a first insulating layer on a main surface of a semiconductor substrate including impurity regions formed therein to have an opening which reaches said impurity region; (b) forming a first conductive layer on the surface of said first insulating layer and inside said opening; (c) forming an opening region which reaches said first insulating layer on the periphery of a region of said first conductive layer to be a lower electrode of one stacked capacitor; (d) selectively forming a mask layer for etching on the surface of said first conductive layer surrounded by said opening region; and (e) etching said first conductive layer using said mask layer for etching as a mask to form a concave part in the surface of said first conductive layer; (B) a dielectric layer on the surface of said first conductive layer; and (C) a second conductive layer on the surface of said dielectric layer.

Claim 11

A storage element for a DRAM comprising: a semiconductor substrate of a first conductivity-type including an impurity region of a second conductivity-type formed therein; an insulating layer formed on a main surface of said semiconductor substrate and having an opening which reaches said impurity region; a capacitor comprising a lower electrode layer including a first part formed along the surface of said insulating layer to be connected through said opening to said impurity region and a second part formed integrally protruding upward from the surface of said first part to surround side surfaces of a space whose section taken along a line perpendicular to the main surface of said semiconductor substrate has an axially symmetrical configuration, a dielectric layer formed on the surface of said lower electrode layer, and an upper electrode layer of the capacitor formed on the surface of said dielectric layer.

Claim 12

A storage element for a DRAM comprising: a semiconductor substrate of a first conductivity-type including an impurity region of a second conductivity-type formed therein; an insulating layer formed on a main surface of said semiconductor substrate and having an opening which reaches said impurity region; a capacitor comprising a lower electrode layer including a first part formed along the surface of said insulating layer to be connected through said opening to said impurity region and a second part formed integrally protruding upward from the surface of said first part to surround side surfaces of a space whose section taken along a line perpendicular to the main surface of said semiconductor substrate has an axially symmetrical configuration, a dielectric layer formed on the surface of said lower electrode layer, and an upper electrode layer of the capacitor formed on the surface of said dielectric layer.

Claim 13

The storage element according to claim 6, wherein said second part of said lower electrode layer has its thickness in a direction parallel to the main surface of said semiconductor substrate changing stepwise.

Claim 14

The storage element according to claim 7, wherein steps are formed at least on the inner peripheral surface of said second part of said lower electrode layer.

Claim 15

The storage element according to claim 7, wherein steps are formed on the inner peripheral surface and the outer peripheral surface of said second part of said lower electrode layer.

Claim 16

The storage element according to claim 6, wherein a region connecting the internal peripheral surface of said second part of said lower electrode layer and the surface of said first part includes a curve surface.

Claim 17

The storage element according to claim 6, wherein the surface of said first part exposed in the bottom part of a concave part of said lower electrode layer surrounded by said second part is formed flat.

Claim 18

A DRAM comprising: a first conductivity-type semiconductor substrate having a main surface and an element isolating region formed on the main surface thereof: a plurality of word lines extending in a prescribed direction on said main surface of said semiconductor substrate; a plurality of bit lines extending in a direction crossing said word lines; a plurality of memory cells formed on said main surface of said semiconductor substrate in a vicinity of a crossing portion of said word lines and said bit lines; each of said plurality of memory cells comprising an access transistor having a pair of second conductivity-type impurity regions formed on said main surface of said semiconductor substrate at a prescribed distance therefrom, and a gate electrode formed on said main surface between said impurity regions with a gate insulating film interposed, and a capacitor comprising a lower electrode layer including a first part formed along the surface of an insulating layer covering at least said gate electrode of said access transistor and connected through an opening formed in said insulating layer to one of said impurity regions of said access transistor and a second part formed integrally protruding upward from the surface of said first part to surround side surfaces of a space whose section taken along a line perpendicular to the main surface of said semiconductor substrate has an axially symmetrical configuration, a dielectric layer formed on the surface of said lower electrode layer, and an upper electrode layer formed on the surface of said dielectric layer.

Claim 19

A DRAM comprising: a first conductivity-type semiconductor substrate having a main surface and an element isolating region formed on the main surface thereof: a plurality of word lines extending in a prescribed direction on said main surface of said semiconductor substrate; a plurality of bit lines extending in a direction crossing said word lines; a plurality of memory cells formed on said main surface of said semiconductor substrate in a vicinity of a crossing portion of said word lines and said bit lines; each of said plurality of memory cells comprising an access transistor having a pair of second conductivity-type impurity regions formed on said main surface of said semiconductor substrate at a prescribed distance therefrom, and a gate electrode formed on said main surface between said impurity regions with a gate insulating film interposed, and a capacitor comprising a lower electrode layer including a first part formed along the surface of an insulating layer covering at least said gate electrode of said access transistor and connected through an opening formed in said insulating layer to one of said impurity regions of said access transistor and a second part formed integrally protruding upward from the surface of said first part to surround side surfaces of a space whose section taken along a line perpendicular to the main surface of said semiconductor substrate has an axially symmetrical configuration, a dielectric layer formed on the surface of said lower electrode layer, and an upper electrode layer formed on the surface of said dielectric layer.