US5912844A
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US
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Method for flash EEPROM data writing
Assignee: Macronix International Co Ltd
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Filing: 1998-01-28
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Granted: 1999-06-15
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Expires: 2018-01-28
Abstract
Abstract Method for writing data to a NOR-type flash memory array including loading page data to a bit-latch buffer, programming cells to low threshold voltage V t , and programming cells to high V t . Programming cells to high V t by either: Channel Hot Electron Injection (CHEI) or Source Side Injection (SSI). CHEI releases the band-to-band induced hot hole damage while SSI further reduces the sector size to be the same as page size for NOR-type flash EEPROM memory.
Inventors
- 👤 Chia-Shing Chen
- 👤 Mam-Tsung Wang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 16:28
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3436; G11C16/3454; G11C16/3459; G11C16/10
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
189 words
A method for writing data to a flash memory array, the method comprising: a) loading external page data into a bit-latch buffer; b) setting to-be-programmed-low-cell bitline latches by data load from the bit-latch buffer; c) low-V t -verifying low V t cells bit-by-bit; d) if a bit is verified, resetting the related bit-latch of each cell; e) if a bit is not verified, delivering program pulses to a respective bitline and wordlines; f) repeating steps c), d), and e) until all the low V t cells in this page are low-V t -verified or a retry limit is reached; g) loading complement byte data of the bit-latch buffer into bit latches; h) programming high V t by source edge channel hot electron injection (CHEI); i) high-V t -verifying high V t cells bit-by-bit; j) if a bit is verified, resetting the related bit-latch of each cell; k) if a bit is not verified, delivering program pulses to a respective bitline and wordlines; l) repeating steps i), j), and k) until all the high V t cells in this byte are high-V t -verified or a retry limit is reached.
Claim 2
Independent Claim
189 words
A method for writing data to a flash memory array, the method comprising: a) loading external page data into a bit-latch buffer; b) setting to-be-programmed-low-cell bitline latches by data load from the bit-latch buffer; c) low-V t -verifying low V t cells bit-by-bit; d) if a bit is verified, resetting the related bit-latch of each cell; e) if a bit is not verified, delivering program pulses to a respective bitline and wordlines; f) repeating steps c), d), and e) until all the low V t cells in this page are low-V t -verified or a retry limit is reached; g) loading complement byte data of the bit-latch buffer into bit latches; h) programming high V t by source edge channel hot electron injection (CHEI); i) high-V t -verifying high V t cells bit-by-bit; j) if a bit is verified, resetting the related bit-latch of each cell; k) if a bit is not verified, delivering program pulses to a respective bitline and wordlines; l) repeating steps i), j), and k) until all the high V t cells in this byte are high-V t -verified or a retry limit is reached.
Claim 3
Dependent Claim
86 words
The method of claim 1, wherein the bit-latch buffer is coupled to corresponding bitlines and has a first state and second state, and includes circuits to change bit latch from one state to another state in response to signals on the corresponding bitlines generated in response to a wordline voltage on a selected wordline being one of greater than or equal to, or less than or equal to, the threshold voltage level of a memory cell connected to the selected wordline and to the corresponding bitline.
Claim 4
Dependent Claim
372 words
The method of claim 1, including: using program logic to control the wordline voltage source in the plurality of bit latches to program a set of memory cells connected to a selected wordline, including using control logic which executes a first threshold cycle to set bit latches in the plurality of bit latches to a program state for memory cells coupled to the corresponding bitlines to be programmed to a first threshold voltage and to a do not program state for memory cells coupled to the corresponding bitlines to be left in an erased state, to execute a program cycle including applying a program potential to bitlines coupled to bit latches loaded with the program state, applying a first wordline voltage to the selected wordline, wherein the first wordline voltage corresponds to the first threshold voltage, and setting the state of the plurality of bit latches to the do not program state after applying the first wordline voltage to indicate whether the first threshold voltage has been successfully programmed, and logic to retry the program cycle until all bit latches in the plurality of bit latches are set to the do not program state or until an error condition is encountered; and a second threshold cycle to set bit latches in the plurality of bit latches to the program state for memory cells coupled to the corresponding bitlines to be programmed to a second threshold voltage and to a do not program state for memory cells coupled to the corresponding bitlines to be left in an erased state or left programmed to the first threshold voltage, to execute a program cycle including applying a program potential to bitlines coupled to bit latches loaded with the program state, applying a second wordline voltage to the selected wordline, wherein the second wordline voltage corresponds to the second threshold voltage, and setting the state of the plurality of bit latches to the do not program state after applying the second wordline voltage to indicate whether the second threshold voltage has been successfully programmed, and logic to retry the program cycle until all bit latches in the plurality of bit latches are set to the do not program state or until an error condition is encountered.
Claim 5
Dependent Claim
188 words
The method of claim 3, wherein the control logic further executes: a third threshold cycle to set bit latches in the plurality of bit latches to a program state for memory cells coupled to the corresponding bitlines to be programmed to a third threshold voltage and to a do not program state for memory cells coupled to the corresponding bitlines to be left in an erased state, left programmed to the first threshold voltage, or left programmed to the second threshold voltage, to execute a program cycle including applying a program potential to bitlines coupled to bit latches loaded with the program state, applying a third wordline voltage to the selected wordline, wherein the third wordline voltage corresponds to the third threshold voltage, and setting the state of the plurality of bit latches to the do not program state after applying the third wordline voltage to indicate whether the third threshold voltage has been successfully programmed, and logic to retry the program cycle until all bit latches in the plurality of bit latches are set to the do not program state or until an error condition is encountered.
Claim 6
Dependent Claim
16 words
The method of claim 3, wherein the error condition includes exceeding a maximum number of retries.
Claim 7
Dependent Claim
18 words
The method of claim 3, wherein the program cycle includes applying a negative potential to the selected wordlines.
Claim 8
Dependent Claim
26 words
The method of claim 3, wherein memory cells in the erased state have a threshold level higher than the first threshold level and second threshold level.
Claim 9
Dependent Claim
25 words
The method of claim 1, wherein the bit-latch buffer in step a) is used to keep the data needed later for high V t program.
Claim 10
Dependent Claim
36 words
The method of claim 1, wherein the resetting of low V t cells in step d) is used to avoid the low V t cells to be programmed again as to have negative V t .
Claim 11
Dependent Claim
15 words
The method of claim 1, wherein the program action in step h) is byte-by-byte basis.
Claim 12
Independent Claim
186 words
A method for writing data to flash memory array, comprising the steps of: a) loading external page data into a bit-latch buffer; b) setting to-be-programmed-low-cell bitline latches by data load from the bit-latch buffer; c) low-V t -verifying low V t cells by bit-by-bit; d) if a bit is verified, resetting the related bit-latch of each cell; e) if a bit is not verified, delivering program pulses to a respective bitline and wordlines f) repeating steps c), d), and e) until all the low V t cells in this page are low-V t -verified or a retry limit is reached; g) loading complement byte data of the bit-latch buffer into bit-latches; h) programming high V t by source side injection (SSI); i) high-V t -verifying high V t cells bit-by-bit; j) if a bit is verified, resetting the related bit-latch of each cell; k) if a bit is not verified, delivering program pulses to a respective bitline and word-line; l) repeating steps i), j), and k) until all the high V t cells in this page are high-V t -verified or a retry limit is reached.
Claim 13
Independent Claim
186 words
A method for writing data to flash memory array, comprising the steps of: a) loading external page data into a bit-latch buffer; b) setting to-be-programmed-low-cell bitline latches by data load from the bit-latch buffer; c) low-V t -verifying low V t cells by bit-by-bit; d) if a bit is verified, resetting the related bit-latch of each cell; e) if a bit is not verified, delivering program pulses to a respective bitline and wordlines f) repeating steps c), d), and e) until all the low V t cells in this page are low-V t -verified or a retry limit is reached; g) loading complement byte data of the bit-latch buffer into bit-latches; h) programming high V t by source side injection (SSI); i) high-V t -verifying high V t cells bit-by-bit; j) if a bit is verified, resetting the related bit-latch of each cell; k) if a bit is not verified, delivering program pulses to a respective bitline and word-line; l) repeating steps i), j), and k) until all the high V t cells in this page are high-V t -verified or a retry limit is reached.
Claim 14
Dependent Claim
86 words
The method of claim 11, wherein the bit-latch buffer is coupled to corresponding bitlines and has a first state and second state, and includes circuits to change bit latch from one state to another state in response to signals on the corresponding bitlines generated in response to a wordline voltage on a selected wordline being one of greater than or equal to, or less than or equal to, the threshold voltage level of a memory cell connected to the selected wordline and to the corresponding bitline.
Claim 15
Dependent Claim
372 words
The method of claim 11, including: using program logic to control the wordline voltage source in the plurality of bit latches to program a set of memory cells connected to a selected wordline, including using control logic which executes a first threshold cycle to set bit latches in the plurality of bit latches to a program state for memory cells coupled to the corresponding bitlines to be programmed to a first threshold voltage and to a do not program state for memory cells coupled to the corresponding bitlines to be left in an erased state, to execute a program cycle including applying a program potential to bitlines coupled to bit latches loaded with the program state, applying a first wordline voltage to the selected wordline, wherein the first wordline voltage corresponds to the first threshold voltage, and setting the state of the plurality of bit latches to the do not program state after applying the first wordline voltage to indicate whether the first threshold voltage has been successfully programmed, and logic to retry the program cycle until all bit latches in the plurality of bit latches are set to the do not program state or until an error condition is encountered; and a second threshold cycle to set bit latches in the plurality of bit latches to the program state for memory cells coupled to the corresponding bitlines to be programmed to a second threshold voltage and to a do not program state for memory cells coupled to the corresponding bitlines to be left in an erased state or left programmed to the first threshold voltage, to execute a program cycle including applying a program potential to bitlines coupled to bit latches loaded with the program state, applying a second wordline voltage to the selected wordline, wherein the second wordline voltage corresponds to the second threshold voltage, and setting the state of the plurality of bit latches to the do not program state after applying the second wordline voltage to indicate whether the second threshold voltage has been successfully programmed, and logic to retry the program cycle until all bit latches in the plurality of bit latches are set to the do not program state or until an error condition is encountered.
Claim 16
Dependent Claim
16 words
The method of claim 13, wherein the error condition includes exceeding a maximum number of retries.
Claim 17
Dependent Claim
18 words
The method of claim 13, wherein the program cycle includes applying a negative potential to the selected wordlines.
Claim 18
Dependent Claim
26 words
The method of claim 13, wherein memory cells in the erased state have a threshold level higher than the first threshold level and second threshold level.
Claim 19
Dependent Claim
188 words
The method of claim 11, wherein the control logic further executes: a third threshold cycle to set bit latches in the plurality of bit latches to the program state for memory cells coupled to the corresponding bitlines to be programmed to a third threshold voltage and to a do not program state for memory cells coupled to the corresponding bitlines to be left in an erased state, left programmed to the first threshold voltage, or left programmed to the second threshold voltage, to execute a program cycle including applying a program potential to bitlines coupled to bit latches loaded with the program state, applying a third wordline voltage to the selected wordline, wherein the third wordline voltage corresponds to the third threshold voltage, and setting the state of the plurality of bit latches to the do not program state after applying the third wordline voltage to indicate whether the third threshold voltage has been successfully programmed, and logic to retry the program cycle until all bit latches in the plurality of bit latches are set to the do not program state or until an error condition is encountered.
Claim 20
Dependent Claim
25 words
The method of claim 11, wherein the bit-latch buffer in step a) is used to keep the data needed later for high V t program.
Claim 21
Dependent Claim
36 words
The method of claim 11, wherein the resetting of low V t cells in step d) is used to avoid the low V t cells to be programmed again as to have negative V t .
Claim 22
Dependent Claim
18 words
The method of claim 11, wherein the program action in step h) is done only with page basis.
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2002-06-14 | 2002-12-14 | 2003-06-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-06-14 | 2006-12-14 | 2007-06-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-06-14 | 2010-12-14 | 2011-06-15 | $7700.00 | Window Closed / Lapsed |