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US5910181A
Expired / Lapsed
US
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Semiconductor integrated circuit device comprising synchronous DRAM core and logic circuit integrated into a single chip and method of testing the synchronous DRAM core
Assignee: Renesas Electronics Corp
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Filing: 1997-11-04
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Granted: 1999-06-08
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Expires: 2017-11-04
Abstract
Abstract A semiconductor integrated circuit device includes a logic circuit and a synchronous dynamic random access memory including a core unit, integrated on a single semiconductor chip. The semiconductor integrated circuit device includes a synchronous dynamic random access memory control circuit which receives external control signals for the synchronous dynamic random access memory from the logic circuit, and outputs internal control signals to the core unit of the synchronous dynamic random access memory. For testing of semiconductor integrated circuit device, external test signals are provided through external terminals. The external test signals are selected by a selector, and are provided to the core unit of the synchronous dynamic random access memory for testing.
Inventors
- 👤 Makoto Hatakenaka
- 👤 Akira Yamazaki
- 👤 Shigeki Tomishima
- 👤 Tadato Yamagata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 12:23
CPC Classifications
G; G06; G06F; G06F12/00; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/14; G11C29/16; G06F11/00; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C29/48
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
104 words
A semiconductor integrated circuit device comprising: a logic circuit and a synchronous dynamic random access memory including a core unit, said logic circuit and said synchronous dynamic random access memory being integrated into a single semiconductor chip; and a synchronous dynamic random access memory control circuit receiving external control signals for said synchronous dynamic random access memory from said logic circuit, and outputting signals to said core unit of said synchronous dynamic random access memory wherein the output signals from said synchronous dynamic random access memory control circuit are internal control signals for controlling said core unit of said synchronous dynamic random access memory.
Claim 2
Dependent Claim
104 words
A semiconductor integrated circuit device comprising: a logic circuit and a synchronous dynamic random access memory including a core unit, said logic circuit and said synchronous dynamic random access memory being integrated into a single semiconductor chip; and a synchronous dynamic random access memory control circuit receiving external control signals for said synchronous dynamic random access memory from said logic circuit, and outputting signals to said core unit of said synchronous dynamic random access memory wherein the output signals from said synchronous dynamic random access memory control circuit are internal control signals for controlling said core unit of said synchronous dynamic random access memory.
Claim 3
Dependent Claim
144 words
The semiconductor integrated circuit device according to claim 1 further comprising: external input terminal means for transmitting a first group of internal control signals for said synchronous dynamic random access memory; and select means for supplying internal control signals to said core unit of said synchronous dynamic random access memory, said internal control signals being obtained by selecting either the first group of internal control signals received from said external input terminal means or a second group of internal control signals received from said synchronous dynamic random access memory control circuit wherein said select means has a first mode selecting the first group of signals received from said external input terminals for testing said semiconductor integrated circuit device with the first group of signals, and a second mode selecting the second group of signals received from said synchronous dynamic random access memory control circuit.
Claim 4
Dependent Claim
157 words
The semiconductor integrated circuit device according to claim 1 further comprising: external input terminal means for transmitting internal control signals for said synchronous dynamic random access memory; synchronizing means for receiving the internal control signals from said external input terminal means and outputting a first group of internal control signals synchronized with a clock signal of said semiconductor integrated circuit; and select means for supplying internal control signals to said core unit of said synchronous dynamic random access memory; said internal control signals being obtained by selecting either the first group of internal control signals received from said synchronizing means or a second group of internal control signals received from said synchronous dynamic random access memory control circuit wherein said select means has a first mode selecting the first group of signals received from said synchronizing means, and a second mode selecting the second group of signals received from said synchronous dynamic random access memory control circuit.
Claim 5
Dependent Claim
161 words
The semiconductor integrated circuit device according to claim 1 further comprising: external input terminal means for transmitting external control signals for said synchronous dynamic random access memory; a command decoder for decoding the external control signals received from said external input terminal means into a first group of internal control signals for controlling said core unit of said synchronous dynamic random access memory; and select means for supplying internal control signals to said core unit of said synchronous dynamic random access memory, the internal control signals being obtained by selecting either the first group of internal control signals received from said command decoder or a second group of internal control signals received from said synchronous dynamic random access memory control circuit, wherein said select means has a first mode selecting the first group of signals received from said command decoder, and a second mode for selecting the second group of signals received from said synchronous dynamic random access memory control circuit.
Claim 6
Dependent Claim
188 words
A semiconductor integrated circuit device according to claim 1 further comprising: external input terminal means for transmitting external control signals for said synchronous dynamic random access memory; synchronizing means for receiving the external control signals from said external input terminal means and outputting external control signals synchronized with a clock signal of said semiconductor integrated circuit; and a command decoder for decoding the external control signals received from said synchronizing means into a first group of internal control signals for controlling said core unit of said synchronous dynamic random access memory; and select means for supplying internal control signals to said core unit of said synchronous dynamic random access memory, the internal control signals being obtained by selecting either the first group of internal control signals received from said command decoder or a second group of internal control signals received from said synchronous dynamic random access memory control circuit, wherein said select means has a first mode selecting the first group of signals received from said command decoder and a second mode selecting the second group of signals received from said synchronous dynamic random access memory control circuit.
Claim 7
Dependent Claim
183 words
The semiconductor integrated circuit device according to claim 1 further comprising: external input terminal means for transmitting external control signals for said synchronous dynamic random access memory; a command decoder for decoding the external control signals received from said external input terminal means into for controlling said core unit of said synchronous dynamic internal control signals random access memory; a synchronizing means receiving the internal control signals from said command decoder for outputting a first group of internal control signals synchronized with a clock signal of said semiconductor integrated circuit; and select means for supplying internal control signals to said core unit of said synchronous dynamic random access memory, the internal control signals being obtained by selecting either the first group of internal control signals received from said synchronizing means or a second group of internal control signals received from said synchronous dynamic random access memory control circuit, wherein said select means has a first mode selecting the first signals received from said synchronizing means and a second mode selecting the second signals received from said synchronous dynamic random access memory control circuit.
Claim 8
Independent Claim
110 words
A method for testing a semiconductor integrated circuit device said test method including the steps of comprising: a logic circuit and a synchronous dynamic random access memory including a core unit, said logic circuit and said synchronous dynamic random access memory being integrated into a single semiconductor chip; and providing external test signals through external input terminal means to a selector; providing internal control signals from a synchronous dynamic random access memory control circuit to a selector; and selecting said external test signals from said external input terminal means, using said selector, for providing the selected signals to a core unit of said synchronous dynamic random access memory for testing.
Claim 9
Independent Claim
110 words
A method for testing a semiconductor integrated circuit device said test method including the steps of comprising: a logic circuit and a synchronous dynamic random access memory including a core unit, said logic circuit and said synchronous dynamic random access memory being integrated into a single semiconductor chip; and providing external test signals through external input terminal means to a selector; providing internal control signals from a synchronous dynamic random access memory control circuit to a selector; and selecting said external test signals from said external input terminal means, using said selector, for providing the selected signals to a core unit of said synchronous dynamic random access memory for testing.
Claim 10
Dependent Claim
34 words
The method for testing a semiconductor integrated circuit device according to claim 7, wherein the external test signals are internal control signals for testing said core unit of said synchronous dynamic random access memory.
Claim 11
Dependent Claim
47 words
The method for testing a semiconductor integrated circuit device according to claim 7, wherein the external test signals are external control signals for said core unit of said synchronous dynamic random access memory, and is decoded by a decoder to internal control signals provided to said selector.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-06-07 | 2002-12-07 | 2003-06-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-06-07 | 2006-12-07 | 2007-06-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-06-07 | 2010-12-07 | 2011-06-08 | $7700.00 | Window Closed / Lapsed |