Thin film transistor and manufacturing method of the thin film transistor

Claim 1

A method of manufacturing a thin film transistor comprising the steps of: depositing a doped amorphous Si layer onto a substrate; removing a portion of the doped amorphous Si layer to provide an exposed area for accommodating a channel region; depositing an amorphous SiGe thin film on the exposed portion of the substrate to form said channel region; irradiating said channel region with energy beams to crystallize said SiGe thin film.

Claim 2

A method of manufacturing a thin film transistor comprising the steps of: depositing a doped amorphous Si layer onto a substrate; removing a portion of the doped amorphous Si layer to provide an exposed area for accommodating a channel region; depositing an amorphous SiGe thin film on the exposed portion of the substrate to form said channel region; irradiating said channel region with energy beams to crystallize said SiGe thin film.

Claim 8

A method of manufacturing a semiconductor device comprising the following steps: providing a substrate; depositing a doped amorphous Si layer onto the substrate; removing a portion of the amorphous Si layer to provide an exposed area on the substrate for accommodating a channel region; depositing an amorphous SiGe layer over the exposed area of the substrate, irradiating the amorphous SiGe and Si layers to crystallize said amorphous SiGe and Si layers and to provide crystallized SiGe and Si layers; depositing an insulating layer onto the crystallized SiGe and Si layers; boring at least a first contact hole and a second contact hole through the insulating layer to the crystallized Si layer, the fist and second contact holes being disposed on opposing sides of the channel region, depositing electrode material into the first and second contact holes to form source and drain electrodes, depositing a gate electrode over the channel region.

Claim 9

A method of manufacturing a semiconductor device comprising the following steps: providing a substrate; depositing a doped amorphous Si layer onto the substrate; removing a portion of the amorphous Si layer to provide an exposed area on the substrate for accommodating a channel region; depositing an amorphous SiGe layer over the exposed area of the substrate, irradiating the amorphous SiGe and Si layers to crystallize said amorphous SiGe and Si layers and to provide crystallized SiGe and Si layers; depositing an insulating layer onto the crystallized SiGe and Si layers; boring at least a first contact hole and a second contact hole through the insulating layer to the crystallized Si layer, the fist and second contact holes being disposed on opposing sides of the channel region, depositing electrode material into the first and second contact holes to form source and drain electrodes, depositing a gate electrode over the channel region.

Claim 14

A method of manufacturing a semiconductor device comprising the following steps: providing a substrate; depositing a doped amorphous Si layer onto the substrate; removing a portion of the amorphous Si layer to provide an exposed area on the substrate for accommodating a channel region; depositing an amorphous SiGe layer over the exposed area of the substrate, irradiating the amorphous SiGe layer and the doped amorphous Si layer to crystallize said amorphous SiGe layer and said amorphous Si layer and to provide a crystallized SiGe layer having a carrier mobility of about 1700 cm 2 /volt at a temperature of about 300K and a crystallized Si layer; depositing a single insulating layer onto the crystallized SiGe layer and the crystallized Si layer; boring at least a first contact hole and a second contact hole through the insulating layer to the crystallized Si layer and on opposing sides of the channel region, depositing electrode material into the first and second contact holes to form source and drain electrodes on opposing sides of the channel region, depositing a gate electrode on top of the channel region.

Claim 15

A method of manufacturing a semiconductor device comprising the following steps: providing a substrate; depositing a doped amorphous Si layer onto the substrate; removing a portion of the amorphous Si layer to provide an exposed area on the substrate for accommodating a channel region; depositing an amorphous SiGe layer over the exposed area of the substrate, irradiating the amorphous SiGe layer and the doped amorphous Si layer to crystallize said amorphous SiGe layer and said amorphous Si layer and to provide a crystallized SiGe layer having a carrier mobility of about 1700 cm 2 /volt at a temperature of about 300K and a crystallized Si layer; depositing a single insulating layer onto the crystallized SiGe layer and the crystallized Si layer; boring at least a first contact hole and a second contact hole through the insulating layer to the crystallized Si layer and on opposing sides of the channel region, depositing electrode material into the first and second contact holes to form source and drain electrodes on opposing sides of the channel region, depositing a gate electrode on top of the channel region.