Patent US5908315A successfully refreshed from Google Patents.
US5908315A
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US
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Method for forming a test structure to determine the effect of LDD length upon transistor performance
Assignee: Advanced Micro Devices Inc
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Filing: 1997-08-18
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Granted: 1999-06-01
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Expires: 2017-08-18
Abstract
Abstract The present invention advantageously provides a method for forming a test structure for determining how LDD length of a transistor affects transistor characteristics. In one embodiment, a first polysilicon gate conductor is provided which is laterally spaced from a second polysilicon gate conductor. The gate conductors are each disposed upon a gate oxide lying above a silicon-based substrate. An LDD implant is forwarded into exposed regions of the substrate to form LDD areas within the substrate adjacent to the gate conductors. A first spacer material is then formed upon sidewall surfaces of both gate conductors to a first pre-defined thickness. Source/drain regions are formed exclusively within the substrate a spaced distance from the first gate conductor, the spaced distance being dictated by the first pre-defined thickness. A second spacer material is formed laterally adjacent to the first spacer material to a second pre-defined distance. Source/drain regions are then formed within the substrate a spaced distance from the second gate conductor, the spaced distance being dictated by the second predefined thickness. The resulting transistors have a mutual source/drain region between them. More transistors may also be fabricated in a similar manner.
Inventors
- 👤 Mark I Gardner
- 👤 Fred N. Hause
- 👤 H. Jim Fulford, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 16:00
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/60; H10D30/601; H10D64/00; H10D64/01; H10D64/021; H10P; H10P74/00; H10P74/27; H10P74/277; Y; Y10; Y10S; Y10S257/00; Y10S257/90
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
158 words
A method for forming a transistor test structure, comprising: providing a first gate conductor and a second gate conductor laterally spaced from each other across a semiconductor topography, said first gate conductor extending above a first channel area and between a first pair of sidewall surfaces and said second gate conductor extending above a second channel area and between a second pair of sidewall surfaces; implanting a lightly doped drain area into said semiconductor topography exclusive of said first and second channel areas; forming a first spacer extending laterally from said first and second pair of sidewall surfaces; implanting a first source and drain area into said semiconductor topography a first distance from said first channel area corresponding to said first spacer; forming a second spacer extending laterally from said first spacer; implanting a second source and drain area into said semiconductor topography a second distance from said second channel area corresponding to said first and second spacers.
Claim 2
Independent Claim
158 words
A method for forming a transistor test structure, comprising: providing a first gate conductor and a second gate conductor laterally spaced from each other across a semiconductor topography, said first gate conductor extending above a first channel area and between a first pair of sidewall surfaces and said second gate conductor extending above a second channel area and between a second pair of sidewall surfaces; implanting a lightly doped drain area into said semiconductor topography exclusive of said first and second channel areas; forming a first spacer extending laterally from said first and second pair of sidewall surfaces; implanting a first source and drain area into said semiconductor topography a first distance from said first channel area corresponding to said first spacer; forming a second spacer extending laterally from said first spacer; implanting a second source and drain area into said semiconductor topography a second distance from said second channel area corresponding to said first and second spacers.
Claim 3
Dependent Claim
42 words
The method of claim 1, further comprising patterning a first masking layer across said second gate conductor prior to implanting the first source and drain area and thereafter removing said first making layer subsequent to forming said first source and drain regions.
Claim 4
Dependent Claim
42 words
The method of claim 1, further comprising forming a second masking layer across said first gate conductor prior to forming said second source and drain area and thereafter removing said second making layer subsequent to forming said second source and drain regions.
Claim 5
Dependent Claim
20 words
The method of claim 1, wherein said first distance is substantially equivalent to the lateral extension of said first spacer.
Claim 6
Dependent Claim
22 words
The method of claim 1, wherein said second distance is substantially equivalent to the lateral extension of said first and second spacers.
Claim 7
Dependent Claim
40 words
The method of claim 1, wherein one of said first source and drain area contacts one of said second source and drain area, thereby forming a mutual implant region interposed between said first gate conductor and said second gate conductor.
Claim 8
Dependent Claim
21 words
The method of claim 1, wherein said forming the first and second spacers occur using dissimilar spacer material from each other.
Claim 9
Dependent Claim
21 words
The method of claim 1, wherein said forming the first and second spacers occur at dissimilar lateral thicknesses from each other.
Claim 10
Dependent Claim
94 words
The method of claim 1, further comprising: providing a third gate conductor laterally spaced from said first and second gate conductors, said third gate conductor extending above a third channel area between a third pair of sidewall surfaces; forming said first spacer concurrently upon said first, second and third pairs of sidewall surfaces; forming a third spacer extending laterally from said first and second second spacers; and implanting a third source and drain area into said semiconductor topography a third distance from said third channel area corresponding to said first, second and third spacers.
References Cited (Backward Citations)
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2002-05-31 | 2002-11-30 | 2003-06-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-05-31 | 2006-11-30 | 2007-06-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-05-31 | 2010-11-30 | 2011-06-01 | $7700.00 | Window Closed / Lapsed |