Fabrication method for reduced-dimension FET devices

Claim 2

In a method for fabricating source drain junctions of an MOSFET on a semiconductor substrate with a crystalline semiconductor surface layer, wherein said method comprises the steps of: (a) amorphizing a portion of said crystalline semiconductor surface layer of said substrate to create an amorphized surface layer with a designed amorphization depth; (b) depositing or implanting an amount of a doping material as a film on said amorphized surface layer to achieve a designed impurity level in said amorphized surface layer; and (c) heating at least a portion of said amorphized surface layer to a temperature sufficient to melt said amorphized surface layer and insufficient to melt said crystalline semiconductor surface layer resulting in said film of doping material diffusing into said melted amorphized surface layer with said amorphized surface layer recrystallizing upon cooling.

Claim 3

The method defined in claim 1, wherein said semiconductor substrate is a crystalline semiconductor material.

Claim 4

The method defined in claim 1, wherein step (a) comprises the step of: (d) implanting atoms of an appropriate element at a designed concentration per unit area with said atoms having been ionized and accelerated to a sufficient energy level by an ion implanter.

Claim 5

The method defined in claim 3, wherein said element is germanium.

Claim 6

The method defined in claim 3, wherein said concentration per unit area of said element is substantially 2×10 14 atoms/cm 2 and said energy level is substantially 20 KeV.

Claim 7

The method defined in claim 3, wherein said concentration per unit area of said element is substantially 6×10 14 atoms/cm 2 and said energy level is substantially 40 KeV.

Claim 8

The method defined in claim 1, wherein step (b) comprises the step of: (d) employing radiation from a laser to decompose said doping material into a gaseous form that is deposited in solid form as said film on said amorphized surface layer.

Claim 9

The method defined in claim 1, wherein step (c) comprises the step of: (d) employing a an appropriate level of radiant fluence from a laser to effect said heating of at least said amorphized surface layer.

Claim 10

The method defined in claim 8, wherein said level of radiant fluence from said laser is substantially 0.4 Joules per cm 2 .

Claim 11

The method defined in claim 8, wherein step (d) comprises the step of: (e) applying a single one of successive pulses of radiant energy from a pulsed laser to an irradiated area of said amorphized surface layer to heat said irradiated area for a duration of that single one of said successive pulses, the radiation energy of that single one of said successive pulses being sufficient to heat said irradiated area of the underlying amorphized surface layer to the melting temperature of said amorphized surface layer and insufficient to heat said crystalline semiconductor surface layer to the melting temperature of said crystalline semiconductor surface layer.

Claim 12

In an integrated circuit fabrication method for fabricating MOSFETs on a semiconductor substrate, wherein adjacent FETs are separated from one another by isolation elements and each fabricated FET comprises (1) a semiconductor gate built up over (2) the surface of an appropriately-doped single crystalline semiconductor well, (3) first and second sidewall spacers situated, respectively, on either side of said semiconductor gate, (4) a relatively deep appropriately-doped single crystalline semiconductor source extending longitudinally from a first isolation element to a part adjacent to said first sidewall spacer, (5) a relatively deep appropriately-doped semiconductor drain extending longitudinally from a second isolation element to a part adjacent to said second sidewall spacer, (6) a first ultra-shallow semiconductor extension situated under said first sidewall spacer for connecting said source to a gate edge proximate thereto, and (7) a second ultra-shallow semiconductor extension situated under said second sidewall spacer for connecting said drain to a gate edge proximate thereto; wherein said method comprises the following steps for fabricating each of said first and second ultra-shallow, doped semiconductor extensions subsequent to the fabrication of said well and said semiconductor gate and prior to the fabrication of said first and second sidewall spacers: (a) ion implanting atoms of an appropriate element in each of first and second surface layers of said single crystalline semiconductor well that extend longitudinally from a gate edge of said semiconductor gate to an isolation element at a designed concentration per unit area and at an appropriate energy level to amorphize said first and second layers to a certain depth which is less than 100 nm deep; (b) depositing an amount of doping material to dope said extensions as a film in solid form on said first and second amorphized surface layers by decomposing an appropriate dopant compound in gaseous form with radiation to achieve a designed impurity level in said first and second amorphized surface layers; (c) applying a first pulse of a number of successive pulses of radiant energy from a pulsed laser to each of said of first and second amorphized surface layers to heat a first area for a duration of said first of said successive pulses, and thereafter serially applying other of said successive pulses of radiant energy from said pulsed laser to other areas of said first and second amorphized surface layers with each successive area overlapping the previous irradiated area of said first or second amorphized surface layer to heat each of said other areas for the duration of a single one of said successive pulses, the radiation energy of each separate one of said successive pulses being sufficient to heat said first or second amorphized surface layer in said area irradiated thereby to the melting temperature of said first or second amorphized surface layer and insufficient to heat said underlying crystalline semiconductor to the melting temperature of said underlying crystalline semiconductor; and (d) providing a time interval between the application of each successive pulse sufficient to permit the melted area of said first or second amorphized surface layers to recrystallize and cool to an initial temperature prior to the application of a successive pulse to said first or second amorphized surface layer.

Claim 13

In an integrated circuit fabrication method for fabricating MOSFETs on a semiconductor substrate, wherein adjacent FETs are separated from one another by isolation elements and each fabricated FET comprises (1) a semiconductor gate built up over (2) the surface of an appropriately-doped single crystalline semiconductor well, (3) first and second sidewall spacers situated, respectively, on either side of said semiconductor gate, (4) a relatively deep appropriately-doped single crystalline semiconductor source extending longitudinally from a first isolation element to a part adjacent to said first sidewall spacer, (5) a relatively deep appropriately-doped semiconductor drain extending longitudinally from a second isolation element to a part adjacent to said second sidewall spacer, (6) a first ultra-shallow semiconductor extension situated under said first sidewall spacer for connecting said source to a gate edge proximate thereto, and (7) a second ultra-shallow semiconductor extension situated under said second sidewall spacer for connecting said drain to a gate edge proximate thereto; wherein said method comprises the following steps for fabricating each of said first and second ultra-shallow, doped semiconductor extensions subsequent to the fabrication of said well and said semiconductor gate and prior to the fabrication of said first and second sidewall spacers: (a) ion implanting atoms of an appropriate element in each of first and second surface layers of said single crystalline semiconductor well that extend longitudinally from a gate edge of said semiconductor gate to an isolation element at a designed concentration per unit area and at an appropriate energy level to amorphize said first and second layers to a certain depth which is less than 100 nm deep; (b) depositing an amount of doping material to dope said extensions as a film in solid form on said first and second amorphized surface layers by decomposing an appropriate dopant compound in gaseous form with radiation to achieve a designed impurity level in said first and second amorphized surface layers; (c) applying a first pulse of a number of successive pulses of radiant energy from a pulsed laser to each of said of first and second amorphized surface layers to heat a first area for a duration of said first of said successive pulses, and thereafter serially applying other of said successive pulses of radiant energy from said pulsed laser to other areas of said first and second amorphized surface layers with each successive area overlapping the previous irradiated area of said first or second amorphized surface layer to heat each of said other areas for the duration of a single one of said successive pulses, the radiation energy of each separate one of said successive pulses being sufficient to heat said first or second amorphized surface layer in said area irradiated thereby to the melting temperature of said first or second amorphized surface layer and insufficient to heat said underlying crystalline semiconductor to the melting temperature of said underlying crystalline semiconductor; and (d) providing a time interval between the application of each successive pulse sufficient to permit the melted area of said first or second amorphized surface layers to recrystallize and cool to an initial temperature prior to the application of a successive pulse to said first or second amorphized surface layer.

Claim 14

The method defined in claim 11, wherein said concentration per unit area of said ion-implanted atoms is substantially 2×10 14 atoms/cm 2 and said energy level is substantially 20 KeV.

Claim 15

The method defined in claim 11, wherein said ion implanted atoms are germanium.

Claim 16

The method defined in claim 13, wherein said concentration per unit area of said ion-implanted germanium atoms is substantially 2×10 14 atoms/cm 2 and said energy level is substantially 20 KeV with the amorphized depth of said first and second layers being substantially 300 Å.

Claim 17

The method defined in claim 11, further wherein step (a) further comprises ion implanting germanium atoms in an upper surface layer of said polycrystalline semiconductor gate at a designed concentration per unit area and at a sufficient energy level to amorphize said upper surface layer of said polycrystalline semiconductor gate to a depth of substantially 300 Å.

Claim 18

The method defined in claim 11, further comprising the following steps for fabricating each of said relatively deep appropriately-doped semiconductor source and drain subsequent to the fabrication of said first and second sidewall spacers: (a) ion implanting atoms at a concentration of substantially 6×10 14 atoms/cm 2 and at an energy level of 40 KeV in each of (1) a source layer that extends longitudinally from an edge of said first sidewall spacer to an isolation element and (2) a drain layer that extends longitudinally from an edge of said second sidewall spacer to an isolation element resulting in the amorphization of said source and drain layers to a relatively deep depth; (b) depositing a an amount of doping material to dope said source and drain layers as a film in solid form on the surface of said amorphized source and drain layers by photolytically decomposing an appropriate dopant compound in gaseous form to achieve a desired impurity level in said amorphized source and drain layers; (c) applying a first of a selected number of successive pulses of radiant energy from a pulsed laser to each of said amorphized source and drain layers to heat a first area for a duration of said first of said successive pulses, and thereafter serially applying other successive pulses of radiant energy from said pulsed laser to other areas of said amorphized layers that at least partially overlaps the previous irradiated area to heat said each of said other areas for the duration of a single one of said successive pulses, the radiation energy of each separate one of said successive pulses being sufficient to heat said amorphized layers in said area irradiated thereby to the melting temperature of said amorphized layers and insufficient to heat said underlying crystalline semiconductor to the melting temperature of said underlying crystalline semiconductor; and (d) providing a time interval between the application of each successive pulse sufficient to permit the melted area of said amorphized layers to recrystallize and cool to an initial temperature prior to the application of a successive pulse to said amorphized layers.

Claim 19

The method defined in claim 16, further comprising: (e) repeating steps (c) and (d) for other parts of said amorphized layers.

Claim 20

The method defined in claim 15, further comprising: (e) repeating steps (c) and (d) for other parts of said amorphized layers.

Claim 21

In the method defined in claim 1 said semiconductor substrate is silicon.

Claim 22

In the method defined in claim 2 said semiconductor substrate is silicon.

Claim 23

In the method defined in claim 3 said semiconductor substrate is silicon.

Claim 24

In the method defined in claim 4 said semiconductor substrate is silicon.

Claim 25

In the method defined in claim 5 said semiconductor substrate is silicon.

Claim 26

In the method defined in claim 6 said semiconductor substrate is silicon.

Claim 27

In the method defined in claim 7 said semiconductor substrate is silicon.

Claim 28

In the method defined in claim 8 said semiconductor substrate is silicon.

Claim 29

In the method defined in claim 9 said semiconductor substrate is silicon.

Claim 30

In the method defined in claim 10 said semiconductor substrate is silicon.

Claim 31

In the method defined in claim 11 said semiconductor substrate is silicon.

Claim 32

In the method defined in claim 12 said semiconductor substrate is silicon.

Claim 33

In the method defined in claim 13 said semiconductor substrate is silicon.

Claim 34

In the method defined in claim 14 said semiconductor substrate is silicon.

Claim 35

In the method defined in claim 15 said semiconductor substrate is silicon.

Claim 36

In the method defined in claim 16 said semiconductor substrate is silicon.

Claim 37

In the method defined in claim 17 said semiconductor substrate is silicon.

Claim 38

In the method defined in claim 18 said semiconductor substrate is silicon.

Claim 39

The method defined in claim 3, wherein said semiconductor layer is silicon, said element is germanium, and said concentration per unit area is substantially 2×10 14 atoms/cm 2 and said energy level is substantially 20 KeV.

Claim 40

The method defined in claim 3, wherein said semiconductor layer is silicon, said element is germanium, and said concentration per unit area is substantially 6×10 14 atoms/cm 2 and said energy level is substantially 40 KeV.