US5907714A
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US
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Method for pipelined data processing with conditioning instructions for controlling execution of instructions without pipeline flushing
Assignee: Texas Instruments Inc
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Filing: 1994-08-19
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Granted: 1999-05-25
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Expires: 2014-08-19
Abstract
Abstract A data processing device includes a circuit having status conditions wherein a particular set of the status conditions can occur in operation of the circuit. An instruction register operates to hold a branch instruction conditional on a particular set of the status conditions. A decoder is connected to the instruction register and the circuit. A program counter is coupled to the decoder wherein the decoder is operable to enter a branch address into the program counter in response to the branch instruction when the particular set of the status conditions of the circuit are present.
Inventors
- 👤 Frederic Boutaud
- 👤 Peter N. Ehlig
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 17:25
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318536; G06; G06F; G06F11/00; G06F11/36; G06F11/362; G06F11/3648; G06F11/3652; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/3005; G06F9/30058; G06F9/30072; G06F9/30094; G06F9/32; G06F9/322; G06F9/323; G06F9/325; G01R31/318505; G06F11/22; G06F11/26; G06F11/273; G06F11/2733
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
182 words
A method for pipelined data processing within a data processing device or system including at least one conditional instruction, comprising: decoding a conditional instruction within an instruction pipeline; conditioning the execution of a predetermined set of conditioned instructions following said conditional instruction within said instruction pipeline in response to a condition specified in said conditional instruction; determining which status conditions of a set of predetermined status conditions have been selected by said conditional instruction with mask bits representative of said predetermined status conditions; making a multiple status test in a single cycle by enabling testing of selected status conditions selected by said mask bits and ignoring status conditions not selected by said mask bits; comparing an actual value each of said selected status conditions to a predetermined value contained in corresponding said status bits of the conditional instruction; and determining which values are required by said conditional instruction for said selected set of predetermined status conditions with status bits representative of said predetermined values; and executing said set of conditioned instructions in response to said conditional instruction without flushing said instruction pipeline.
Claim 2
Independent Claim
182 words
A method for pipelined data processing within a data processing device or system including at least one conditional instruction, comprising: decoding a conditional instruction within an instruction pipeline; conditioning the execution of a predetermined set of conditioned instructions following said conditional instruction within said instruction pipeline in response to a condition specified in said conditional instruction; determining which status conditions of a set of predetermined status conditions have been selected by said conditional instruction with mask bits representative of said predetermined status conditions; making a multiple status test in a single cycle by enabling testing of selected status conditions selected by said mask bits and ignoring status conditions not selected by said mask bits; comparing an actual value each of said selected status conditions to a predetermined value contained in corresponding said status bits of the conditional instruction; and determining which values are required by said conditional instruction for said selected set of predetermined status conditions with status bits representative of said predetermined values; and executing said set of conditioned instructions in response to said conditional instruction without flushing said instruction pipeline.
Claim 3
Dependent Claim
31 words
The method of claim 1, wherein said conditioning step further comprises, allowing normal execution of said conditioned instructions based on a logical combination of said mask bits and said status bits.
Claim 4
Dependent Claim
53 words
The method of claim 1, wherein said executing step further comprises executing said set of conditioned instructions in a normal manner if said condition specified in said conditional instruction is present, or by changing said conditioned instructions to a no-operation (NOP) instruction if said condition specified in said conditional instruction is not present.
Claim 5
Independent Claim
175 words
A method for pipelined data processing within a data processing device or system including at least one conditional instruction, comprising: decoding a conditional instruction within an instruction pipeline; conditioning the execution of a predetermined set of conditioned instructions following said conditional instruction within said instruction pipeline in response to a condition specified in said conditional instruction; determining which status conditions of a set of predetermined status conditions have been selected by said conditional instruction with mask bits representative of said predetermined status conditions; wherein said conditional instruction includes a pair of bits corresponding to each of said status conditions of said set of predetermined status conditions; wherein said determining said condition step further comprises using a first of said pair of bits for determining whether to consider a status condition; wherein said conditioning step further comprises using a second of said pair of bits as a level to test said actual value of said status condition against; and executing said set of conditioned instructions in response to said conditional instruction without flushing said instruction pipeline.
Claim 6
Independent Claim
175 words
A method for pipelined data processing within a data processing device or system including at least one conditional instruction, comprising: decoding a conditional instruction within an instruction pipeline; conditioning the execution of a predetermined set of conditioned instructions following said conditional instruction within said instruction pipeline in response to a condition specified in said conditional instruction; determining which status conditions of a set of predetermined status conditions have been selected by said conditional instruction with mask bits representative of said predetermined status conditions; wherein said conditional instruction includes a pair of bits corresponding to each of said status conditions of said set of predetermined status conditions; wherein said determining said condition step further comprises using a first of said pair of bits for determining whether to consider a status condition; wherein said conditioning step further comprises using a second of said pair of bits as a level to test said actual value of said status condition against; and executing said set of conditioned instructions in response to said conditional instruction without flushing said instruction pipeline.
Claim 7
Independent Claim
283 words
A method for pipelined data processing within a data processing device or system including at least one conditional instruction, comprising: a) decoding a conditional instruction within an instruction pipeline; wherein said conditional instruction includes a plurality of pairs of bits corresponding to a set of predetermined status conditions such that each said pair of bits comprises a mask bit and a status bit; b) conditioning the execution of a predetermined set of conditioned instructions following said conditional instruction within said instruction pipeline in response to a condition specified in said conditional instruction; (c) determining which status conditions of said set of predetermined status conditions have been selected by said conditional instruction to form said condition by using a first of said pair of bits as said mask bit representative of said predetermined status conditions for determining whether to consider said status condition; wherein said determining step further comprises making a multiple status test in a single cycle by enabling testing of selected status conditions selected by said mask bits and ignoring status conditions not selected by said mask bits; (d) using a second of said pair of bits as a level to test said actual value of said status condition against by comparing an actual value of each of said selected status conditions to a predetermined value contained in corresponding said status bits of the conditional instruction; and (e) executing said set of conditioned instructions without flushing said instruction pipeline by executing said set of conditioned instructions in a normal manner if said condition specified in said conditional instruction is present, or by changing said conditioned instructions to a no-operation (NOP) instruction if said condition specified in said conditional instruction is not present.
Claim 8
Independent Claim
283 words
A method for pipelined data processing within a data processing device or system including at least one conditional instruction, comprising: a) decoding a conditional instruction within an instruction pipeline; wherein said conditional instruction includes a plurality of pairs of bits corresponding to a set of predetermined status conditions such that each said pair of bits comprises a mask bit and a status bit; b) conditioning the execution of a predetermined set of conditioned instructions following said conditional instruction within said instruction pipeline in response to a condition specified in said conditional instruction; (c) determining which status conditions of said set of predetermined status conditions have been selected by said conditional instruction to form said condition by using a first of said pair of bits as said mask bit representative of said predetermined status conditions for determining whether to consider said status condition; wherein said determining step further comprises making a multiple status test in a single cycle by enabling testing of selected status conditions selected by said mask bits and ignoring status conditions not selected by said mask bits; (d) using a second of said pair of bits as a level to test said actual value of said status condition against by comparing an actual value of each of said selected status conditions to a predetermined value contained in corresponding said status bits of the conditional instruction; and (e) executing said set of conditioned instructions without flushing said instruction pipeline by executing said set of conditioned instructions in a normal manner if said condition specified in said conditional instruction is present, or by changing said conditioned instructions to a no-operation (NOP) instruction if said condition specified in said conditional instruction is not present.
Claim 9
Dependent Claim
31 words
The method of claim 5, wherein said conditioning step further comprises allowing normal execution of said conditioned instructions based on a logical combination of said mask bits and said status bits.
Claim 10
Independent Claim
234 words
A method for pipelined data processing within a data processing device or system including at least one conditional instruction, comprising: fetching a conditional instruction from a first address in a memory which is associated with said data processing device; fetching a conditioned instruction from a second address in said memory while said conditional instruction is being processed within an instruction pipeline of said data processing device; fetching a third instruction from a third address in said memory while said conditional instruction and said conditioned instruction are being processed within said instruction pipeline; wherein said first address, said second address and said third address are sequential addresses within said memory; executing said conditional instruction by determining if a condition specified by said conditional instruction is true by enabling testing of selected status conditions selected by a set of mask bits included in said conditional instruction and ignoring status conditions not selected by said mask bits; conditioning the execution of said conditioned instruction within said instruction pipeline in response to said condition, by executing said conditioned instruction in a normal manner if said condition is true and by ignoring any result of said conditioned instruction if said condition is false; and executing said third instruction in a normal manner without regard to the step of executing said conditional instruction, whereby sequential instruction processing proceeds and said conditioned instruction is conditionally executed without flushing said instruction pipeline.
Claim 11
Independent Claim
234 words
A method for pipelined data processing within a data processing device or system including at least one conditional instruction, comprising: fetching a conditional instruction from a first address in a memory which is associated with said data processing device; fetching a conditioned instruction from a second address in said memory while said conditional instruction is being processed within an instruction pipeline of said data processing device; fetching a third instruction from a third address in said memory while said conditional instruction and said conditioned instruction are being processed within said instruction pipeline; wherein said first address, said second address and said third address are sequential addresses within said memory; executing said conditional instruction by determining if a condition specified by said conditional instruction is true by enabling testing of selected status conditions selected by a set of mask bits included in said conditional instruction and ignoring status conditions not selected by said mask bits; conditioning the execution of said conditioned instruction within said instruction pipeline in response to said condition, by executing said conditioned instruction in a normal manner if said condition is true and by ignoring any result of said conditioned instruction if said condition is false; and executing said third instruction in a normal manner without regard to the step of executing said conditional instruction, whereby sequential instruction processing proceeds and said conditioned instruction is conditionally executed without flushing said instruction pipeline.
Claim 12
Dependent Claim
39 words
The method of claim 7, wherein said conditional instruction includes a plurality of pairs of bits corresponding to a set of predetermined status conditions such that each said pair of bits comprises a mask bit and a status bit.
Claim 13
Dependent Claim
86 words
The method of claim 8 wherein the step of executing said conditional instruction further comprises determining which status conditions of said set of predetermined status conditions have been selected by said conditional instruction to form said condition by using a first of said pair of bits as said mask bit representative of said predetermined status conditions for determining whether to consider said status condition by enabling testing of selected status conditions selected by said mask bits and ignoring status conditions not selected by said mask bits.
Claim 14
Dependent Claim
62 words
The method of claim 9 wherein the step of executing said conditional instruction further comprises using a second of said pair of bits as a level to test said actual value of said status condition against by comparing an actual value of each of said selected status conditions to a predetermined value contained in corresponding said status bits of the conditional instruction.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-05-24 | 2002-11-23 | 2003-05-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-05-24 | 2006-11-23 | 2007-05-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-05-24 | 2010-11-23 | 2011-05-25 | $7700.00 | Window Closed / Lapsed |