Patent US5035200A successfully refreshed from Google Patents.
Patent US5907697A successfully refreshed from Google Patents.
US5907697A
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US
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Emulation system having a scalable multi-level multi-stage hybrid programmable interconnect network
Assignee: Mentor Graphics Corp
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Filing: 1996-07-30
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Granted: 1999-05-25
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Expires: 2016-07-30
Abstract
Abstract A scalable multi-level multi-stage network topology is employed to interconnect reconfigurable logic elements within the special purpose FPGA, inter-FPGA, inter-logic boards, and inter-backplanes. More specifically, under the presently preferred embodiment, an on-chip 3-stage inter-logic element crossbar network is provided to each special purpose FPGA for interconnecting the reconfigurable logic elements and the I/O pins of the special purpose FPGA. A two level three-stage inter-FPGA hybrid crossbar network is provided to interconnect the special purpose FPGAs and I/O pins of the logic board. The two-level three-stage inter-FPGA hybrid crossbar network consists of two stages of programmable crossbars and one stage of one or more special purpose FPGAs used for interconnection only. The exact number of special purpose FPGAs to be used for interconnection only on a particular logic board is dependent on the specific circuit design being emulated. A two-level two-stage inter-board crossbar network is provided to interconnect the logic boards or I/O boards for interconnecting the logic elements to external devices. Finally, a single-stage inter-backplane network and a number of PCBs are provided to interconnect multi-backplanes to form a multi-crate system.
Inventors
- 👤 Jean Barbier
- 👤 Olivier LePape
- 👤 Frederic Reblewski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 02:53
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/78; G06F15/7867
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
209 words
A method of emulating a circuit design in a system having a plurality of field programmable gate arrays (FPGAs) interconnected with a plurality of routing chips, wherein each FPGA of the plurality of FPGAs includes a plurality of reconfigurable logic elements (LEs), the method comprising the steps of: (a) reserving a number of FPGAs of the plurality of FPGAs to be used for interconnecting unreserved ones of the plurality of FPGAs, wherein each FPGA of the plurality of FPGAs includes an on-chip subset of a first stage of an inter-FPGA network, wherein each of the plurality of routing chips includes an on-chip subset of a second stage of the inter-FPGA network, and wherein the reserved ones of the plurality of FPGAs forms a third stage of the inter-FPGA network; (b) mapping a portion of the circuit design onto the unreserved ones of the plurality of FPGAs; (c) attempting to interconnect the reconfigurable LEs of the unreserved ones of the plurality of FPGAs in accordance with the circuit design; (d) increasing the number of reserved ones of the plurality of FPGAs which will only be used for interconnecting the unreserved ones of the plurality of FPGAs responsive to the attempting step (c) failing; and (e) repeating the attempting step (c).
Claim 2
Independent Claim
209 words
A method of emulating a circuit design in a system having a plurality of field programmable gate arrays (FPGAs) interconnected with a plurality of routing chips, wherein each FPGA of the plurality of FPGAs includes a plurality of reconfigurable logic elements (LEs), the method comprising the steps of: (a) reserving a number of FPGAs of the plurality of FPGAs to be used for interconnecting unreserved ones of the plurality of FPGAs, wherein each FPGA of the plurality of FPGAs includes an on-chip subset of a first stage of an inter-FPGA network, wherein each of the plurality of routing chips includes an on-chip subset of a second stage of the inter-FPGA network, and wherein the reserved ones of the plurality of FPGAs forms a third stage of the inter-FPGA network; (b) mapping a portion of the circuit design onto the unreserved ones of the plurality of FPGAs; (c) attempting to interconnect the reconfigurable LEs of the unreserved ones of the plurality of FPGAs in accordance with the circuit design; (d) increasing the number of reserved ones of the plurality of FPGAs which will only be used for interconnecting the unreserved ones of the plurality of FPGAs responsive to the attempting step (c) failing; and (e) repeating the attempting step (c).
Claim 3
Dependent Claim
24 words
The method of claim 1, wherein the increasing step (d) comprises the step of reserving a previously unreserved one of the plurality of FPGAs.
Claim 4
Dependent Claim
202 words
A logic board comprising: a plurality of board input/output (I/O) pins; a first plurality of field programmable gate arrays (FPGAs), each having a plurality of reconfigurable logic elements (LEs) for emulating circuit elements of a circuit design, a plurality of FPGA I/O pins, an on-chip multi-stage inter-LE network of programmable interconnect devices (PIDs) coupled to the FPGA I/O pins and the reconfigurable LEs for selectively interconnecting the reconfigurable LEs to each other and to the FPGA I/O pins, and an on-chip subset of a first stage of an inter-FPGA network of PIDs disposed in between the FPGA I/O pins and the inter-LE network of PIDs for interconnecting the FPGA to other FPGAs and to board I/O pins; a second stage of the inter-FPGA network of PIDs coupled to the FPGAs and the board I/O pins for cooperating with the on-chip first stage of the inter-FPGA network of PIDs distributively implemented on the FPGAs for interconnecting the FPGAs to each other and to the board I/O pins; and a third stage of the inter-FPGA network of PIDs, wherein the third stage comprises at lease one FPGA, and wherein each FPGA of the third stage is used only for interconnecting the plurality of FPGAs.
Claim 5
Dependent Claim
202 words
A logic board comprising: a plurality of board input/output (I/O) pins; a first plurality of field programmable gate arrays (FPGAs), each having a plurality of reconfigurable logic elements (LEs) for emulating circuit elements of a circuit design, a plurality of FPGA I/O pins, an on-chip multi-stage inter-LE network of programmable interconnect devices (PIDs) coupled to the FPGA I/O pins and the reconfigurable LEs for selectively interconnecting the reconfigurable LEs to each other and to the FPGA I/O pins, and an on-chip subset of a first stage of an inter-FPGA network of PIDs disposed in between the FPGA I/O pins and the inter-LE network of PIDs for interconnecting the FPGA to other FPGAs and to board I/O pins; a second stage of the inter-FPGA network of PIDs coupled to the FPGAs and the board I/O pins for cooperating with the on-chip first stage of the inter-FPGA network of PIDs distributively implemented on the FPGAs for interconnecting the FPGAs to each other and to the board I/O pins; and a third stage of the inter-FPGA network of PIDs, wherein the third stage comprises at lease one FPGA, and wherein each FPGA of the third stage is used only for interconnecting the plurality of FPGAs.
Claim 6
Dependent Claim
52 words
The logic board as set forth in claim 3, wherein the second stage of the inter-FPGA network of PIDs comprises a plurality of PIDs coupled to the PIDs at the first stage of the inter-FPGA network for interconnecting the FPGA I/O pins to each other and to the logic board I/O pins.
Claim 7
Dependent Claim
47 words
The logic board as set forth in claim 3, wherein the second stage of the inter-FPGA network of PIDs also serves as a first stage of an inter-logic board network of PIDs for interconnecting the logic board to other logic boards and one or more I/O boards.
Claim 8
Dependent Claim
203 words
A logic board comprising: a plurality of board input/output (I/O) pins; a first plurality of reprogrammable logic devices (RLDs), each having a plurality of reconfigurable logic elements (LEs) for emulating circuit elements of a circuit design, a plurality of RLD I/O pins, an on-chip multi-stage inter-LE network of programmable interconnect devices (PIDs) coupled to the RLD I/O pins and the reconfigurable LEs for selectively interconnecting the reconfigurable LEs to each other and to the RLD I/O pins, and an on-chip subset of a first stage of an inter-RLD network of PIDs disposed in between the RLD I/O pins and the inter-LE network of PIDs for interconnecting the RLD to other RLDs and to board I/O pins; a second stage of the inter-RLD network of PIDs coupled to the RLDs and the board I/O pins for cooperating with the on-chip first stage of the inter-RLD network of PIDs distributively implemented on the RLDs for interconnecting the RLDs to each other and to the board I/O pins; and a third stage of the of the inter-RLD network of PIDs, wherein the third stage comprises at lease one RLD, and wherein each RLD in the third stage is used only for interconnecting the plurality of RLDs.
Claim 9
Dependent Claim
203 words
A logic board comprising: a plurality of board input/output (I/O) pins; a first plurality of reprogrammable logic devices (RLDs), each having a plurality of reconfigurable logic elements (LEs) for emulating circuit elements of a circuit design, a plurality of RLD I/O pins, an on-chip multi-stage inter-LE network of programmable interconnect devices (PIDs) coupled to the RLD I/O pins and the reconfigurable LEs for selectively interconnecting the reconfigurable LEs to each other and to the RLD I/O pins, and an on-chip subset of a first stage of an inter-RLD network of PIDs disposed in between the RLD I/O pins and the inter-LE network of PIDs for interconnecting the RLD to other RLDs and to board I/O pins; a second stage of the inter-RLD network of PIDs coupled to the RLDs and the board I/O pins for cooperating with the on-chip first stage of the inter-RLD network of PIDs distributively implemented on the RLDs for interconnecting the RLDs to each other and to the board I/O pins; and a third stage of the of the inter-RLD network of PIDs, wherein the third stage comprises at lease one RLD, and wherein each RLD in the third stage is used only for interconnecting the plurality of RLDs.
Claim 10
Dependent Claim
52 words
The logic board as set forth in claim 6, wherein the second stage of the inter-RLD network of PIDs comprises a plurality of PIDs coupled to the PIDs at the first stage of the inter-RLD network for interconnecting the RLD I/O pins to each other and to the logic board I/O pins.
Claim 11
Dependent Claim
47 words
The logic board as set forth in claim 6, wherein the second stage of the inter-RLD network of PIDs also serves as a first stage of an inter-logic board network of PIDs for interconnecting the logic board to other logic boards and one or more I/O boards.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-05-24 | 2002-11-23 | 2003-05-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-05-24 | 2006-11-23 | 2007-05-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-05-24 | 2010-11-23 | 2011-05-25 | $7700.00 | Window Closed / Lapsed |