US5907173A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High voltage field effect transistor and method of fabricating the same
Assignee: SK Hynix Inc
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Filing: 1998-08-25
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Granted: 1999-05-25
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Expires: 2018-08-25
Abstract
Abstract The present invention discloses a high voltage field effect transistor and fabricating the same. A high voltage field effect transistor includes a semiconductor substrate, a first conductivity type well in the semiconductor substrate, first and second conductivity type drift regions in the first conductivity type well, heavily doped impurity regions having first and second conductivity types in the first conductivity type drift region, a heavily doped second conductivity type impurity region in the second conductivity type drift region, and a lightly doped second conductivity type buffer layer in the second conductivity type drift region to surround the heavily doped second conductivity type impurity region.
Inventors
- 👤 Oh Kyong Kwon
- 👤 Mueng Ryul Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 12:48
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/601; H10D30/603; H10D30/01; H10D30/021; H10D30/0221; H10D64/00; H10D64/111; H10P; H10P10/00; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D62/17; H10D62/213; H10D62/221; H10D62/235; H10D62/299; H10D62/307; H10D62/351; H10D62/357; H10D62/364; H10D62/378
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
90 words
A high voltage field effect transistor, comprising: a semiconductor substrate; a first conductivity type well in the semiconductor substrate; first and second conductivity type drift regions in the first conductivity type well; heavily doped impurity regions having first and second conductivity types in the first conductivity type drift region; a heavily doped second conductivity type impurity region in the second conductivity type drift region; and a lightly doped second conductivity type buffer layer in the second conductivity type drift region to surround the heavily doped second conductivity type impurity region.
Claim 2
Dependent Claim
90 words
A high voltage field effect transistor, comprising: a semiconductor substrate; a first conductivity type well in the semiconductor substrate; first and second conductivity type drift regions in the first conductivity type well; heavily doped impurity regions having first and second conductivity types in the first conductivity type drift region; a heavily doped second conductivity type impurity region in the second conductivity type drift region; and a lightly doped second conductivity type buffer layer in the second conductivity type drift region to surround the heavily doped second conductivity type impurity region.
Claim 3
Dependent Claim
17 words
The transistor according to claim 1, further comprising a gate electrode over the first conductivity type well.
Claim 4
Dependent Claim
30 words
The transistor according to claim 1, further comprising a source electrode on the heavily doped impurity regions having first and second conductivity types in the first conductivity type drift region.
Claim 5
Dependent Claim
27 words
The transistor according to claim 1, further comprising a drain electrode on the heavily doped second conductivity type impurity region in the second conductivity type drift region.
Claim 6
Dependent Claim
18 words
The transistor according to claim 1, further comprising a field plate over the second conductivity type drift region.
Claim 7
Dependent Claim
22 words
The transistor according to claim 1, wherein the first conductivity type is a p-type and the second conductivity type is an n-type.
Claim 8
Dependent Claim
22 words
The transistor according to claim 1, wherein the first conductivity type is an n-type and the second conductivity type is a p-type.
Claim 9
Dependent Claim
32 words
The transistor according to claim 1, wherein the second conductivity type drift region has a lightly doped drain region at a boundary between the first and the second conductivity type drift regions.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-05-24 | 2002-11-23 | 2003-05-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-05-24 | 2006-11-23 | 2007-05-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-05-24 | 2010-11-23 | 2011-05-25 | $7700.00 | Window Closed / Lapsed |