High voltage metal oxide silicon field effect transistor

Claim 2

A semiconductor device, comprising: a semiconductor substrate; first and second conductive wells formed in said substrate; an isolation membrane formed on the substrate between the first and second conductive wells; gates formed on a surface of the substrate in which the first conductive well is formed, and on the surface of the substrate in which the second conductive well is formed, respectively; drift areas formed in the first and second conductive wells so as to be connected with a lower part of a corresponding gate; drains formed in the drift areas; sources having buried diffusion areas formed in the first and second conductive wells, so as to be connected with a lower part of a corresponding gate; body contacts formed in the first and second conductive wells, and on one side of the source having a buried diffusion area; a first insulation film formed on the substrates, including the gates and the isolation membrane, and having a contact hole formed in such way that surfaces of source and drain are exposed; source/drain electrodes formed in specified parts of the first insulation film including the contact hole; field plates located on the first insulation film in the drift areas and gates, and formed between the source/drain electrodes so as to be separated from the source/drain electrodes; and a second insulation film formed on the first insulation film including the source/drain electrodes and the field plates.

Claim 3

The semiconductor device of claim 1, wherein the field plates, the source electrodes and the drain electrodes are formed of substantially the same type of metal.

Claim 4

The semiconductor device of claim 1, wherein the first conductive well comprises an n-well.

Claim 5

The semiconductor device of claim 1, wherein the second conductive well comprises a p-well.

Claim 6

The semiconductor device of claim 1, wherein each of said gates is 1.2 μm to 1.5 μm in length.

Claim 7

A semiconductor device, comprising: a semiconductor substrate; first and second conductive wells formed in the substrate; gates formed on a surface of the substrate in which the first conductive well is formed, and on a surface of the substrate in which the second conductive well is formed, respectively; first and second drift areas formed in the first conductive well, so as to be connected with lower parts of the first gate, in a form separated from each other at a specified space; first and second drift areas formed in the second conductive well so as to be connected with lower parts of the second gate, in a form separated from each other at a specified space; source/drain formed in the first and second drift areas formed in the first and second conductive wells; a body contact formed in the first and second conductive wells, and on each side of the first and second drift areas between which is an isolation membrane; a first insulation film formed on the substrate, including the gates and isolation membranes, and having a contact hole formed in such way that surfaces of source/drain and body contact are exposed; source/drain electrodes formed in specified parts of the first insulation film including the contact hole; first and second field plates located on the first insulation film formed on the drift areas and gates, and formed between the source/drain electrodes so as to be separated from the source/drain electrodes; and a second insulation film formed on the first insulation film including the source/drain electrodes and the first and second field plates.

Claim 8

A semiconductor device, comprising: a semiconductor substrate; first and second conductive wells formed in the substrate; gates formed on a surface of the substrate in which the first conductive well is formed, and on a surface of the substrate in which the second conductive well is formed, respectively; first and second drift areas formed in the first conductive well, so as to be connected with lower parts of the first gate, in a form separated from each other at a specified space; first and second drift areas formed in the second conductive well so as to be connected with lower parts of the second gate, in a form separated from each other at a specified space; source/drain formed in the first and second drift areas formed in the first and second conductive wells; a body contact formed in the first and second conductive wells, and on each side of the first and second drift areas between which is an isolation membrane; a first insulation film formed on the substrate, including the gates and isolation membranes, and having a contact hole formed in such way that surfaces of source/drain and body contact are exposed; source/drain electrodes formed in specified parts of the first insulation film including the contact hole; first and second field plates located on the first insulation film formed on the drift areas and gates, and formed between the source/drain electrodes so as to be separated from the source/drain electrodes; and a second insulation film formed on the first insulation film including the source/drain electrodes and the first and second field plates.

Claim 9

The semiconductor device of claim 6, wherein the first and second field plates and the source/drain electrodes are formed of substantially the same type of metal.

Claim 10

The semiconductor device of claim 6, wherein said first conductive well comprises an n-well.

Claim 11

The semiconductor device of claim 6, wherein said second conductive well comprises a p-well.

Claim 12

The semiconductor device of claim 6, wherein said gates are each 1.2 μm to 1.5 μm in length.

Claim 13

A semiconductor device, comprising: a semiconductor substrate; a first conductive well formed in the substrate; a gate formed on a surface of the substrate in which the first conductive well is formed; a drift area formed in the first conductive well so as to be connected with a lower part of the gate; a drain formed in the drift area; a source having a buried diffusion area formed in the first conductive well so as to be connected with a lower part of the gate; a body contact formed in the first conductive well, and on a side of the source having a buried diffusion area; a first insulation film formed on the substrate, including the gate, and having a contact hole formed in such way that source and drain surfaces are exposed; source/drain electrodes formed in predetermined parts of the first insulation film including the contact hole; field plates located on the first insulation film formed on the drift area and the gate, and formed between the source/drain electrodes so as to be separated from the source/drain electrodes; and a second insulation film formed on the first insulation film including the source/drain electrodes and field plates.

Claim 14

A semiconductor device, comprising: a semiconductor substrate; a first conductive well formed in the substrate; a gate formed on a surface of the substrate in which the first conductive well is formed; a drift area formed in the first conductive well so as to be connected with a lower part of the gate; a drain formed in the drift area; a source having a buried diffusion area formed in the first conductive well so as to be connected with a lower part of the gate; a body contact formed in the first conductive well, and on a side of the source having a buried diffusion area; a first insulation film formed on the substrate, including the gate, and having a contact hole formed in such way that source and drain surfaces are exposed; source/drain electrodes formed in predetermined parts of the first insulation film including the contact hole; field plates located on the first insulation film formed on the drift area and the gate, and formed between the source/drain electrodes so as to be separated from the source/drain electrodes; and a second insulation film formed on the first insulation film including the source/drain electrodes and field plates.

Claim 15

The semiconductor device of claim 11, wherein said field plates and said source/drain electrodes are formed of substantially the same type of metal.

Claim 16

The semiconductor device of claim 11, wherein said first conductive well comprises one of an n-well and a p-well.

Claim 17

The semiconductor device of claim 11, wherein said gate is 1.2 μm to 1.5 μm in length.

Claim 18

A semiconductor device, comprising: a semiconductor substrate; a first conductive well formed in the substrate; a gate formed on a surface of the substrate in which the first conductive well is formed; first and second drift areas formed in the first conductive well, so as to be connected with lower parts of the gate, in a form separated from each other at a specified space; source/drain formed in the first and second drift areas in the first conductive well; body contacts formed in the first conductive well, and on each side of the first and second drift areas between which is an isolation membrane; a first insulation film formed on the substrate including the gate and isolation membrane, and having a contact hole formed in such way that source/drain and body contact surfaces are exposed; source/drain electrodes formed in predetermined parts of the first insulation film including the contact hole; first and second field plates located on the first insulation film formed in the drift areas and gate, and formed between the source/drain electrodes so as to be separated from the source/drain electrodes; and a second insulation film formed on the first insulation film including the source/drain electrodes and the first and second field plates.

Claim 19

A semiconductor device, comprising: a semiconductor substrate; a first conductive well formed in the substrate; a gate formed on a surface of the substrate in which the first conductive well is formed; first and second drift areas formed in the first conductive well, so as to be connected with lower parts of the gate, in a form separated from each other at a specified space; source/drain formed in the first and second drift areas in the first conductive well; body contacts formed in the first conductive well, and on each side of the first and second drift areas between which is an isolation membrane; a first insulation film formed on the substrate including the gate and isolation membrane, and having a contact hole formed in such way that source/drain and body contact surfaces are exposed; source/drain electrodes formed in predetermined parts of the first insulation film including the contact hole; first and second field plates located on the first insulation film formed in the drift areas and gate, and formed between the source/drain electrodes so as to be separated from the source/drain electrodes; and a second insulation film formed on the first insulation film including the source/drain electrodes and the first and second field plates.

Claim 20

The semiconductor device of claim 15, wherein the first and second field plates and the source/drain electrodes are formed of substantially the same type of metal.

Claim 21

The semiconductor device of claim 15, wherein said first conductive well comprises one of an n-well and a p-well.

Claim 22

The semiconductor device of claim 15, wherein said gate is 1.2 μm to 1.5 μm in length.

Claim 23

A semiconductor device, comprising: a substrate of a first conductivity type; first and second impurity regions of a second conductivity type formed in the substrate; a control electrode insulatively formed between the first and second impurity regions; a first drift area formed in one of the first and second impurity regions; and a first field plate insulatively overlapping a portion of the first drift area.

Claim 24

A semiconductor device, comprising: a substrate of a first conductivity type; first and second impurity regions of a second conductivity type formed in the substrate; a control electrode insulatively formed between the first and second impurity regions; a first drift area formed in one of the first and second impurity regions; and a first field plate insulatively overlapping a portion of the first drift area.

Claim 25

The semiconductor device of claim 19, wherein the control electrode overlaps the first and second impurity regions.

Claim 26

The semiconductor device of claim 19, wherein the first field plate insulatively overlaps the control electrode.

Claim 27

The semiconductor device of claim 19, further comprising a second drift area formed in one of said first and second impurity regions.

Claim 28

The semiconductor device of claim 22, further comprising a second field plate insulatively overlapping a portion of the second drift area.

Claim 29

The semiconductor device of claim 23, wherein the second field plate insulatively overlaps the control electrode.