US5905897A
Expired / Lapsed
US
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Method and apparatus for selecting a nonblocked interrupt request
Assignee: Industrial Technology Research Institute
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Filing: 1997-03-20
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Granted: 1999-05-18
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Expires: 2017-03-20
Abstract
Abstract An interrupt processing method and apparatus particularly well-suited for use in an interrupt controller of a multiprocessor system or device. Each of the interrupt requests has at least one destination processor associated therewith for servicing the interrupt request. An interrupt controller in accordance with the present invention applies latched interrupt requests to a priority compare tree which serves to prioritize received interrupt requests. A number of higher priority requests, including the highest priority request, are supplied to a destination selection circuit which includes an interrupt dispatcher which determines a processor to which the first priority interrupt request will be dispatched. Similar determinations are made for the remaining identified interrupt requests, but with the corresponding destination register contents masked to prevent processors already selected to receive a higher priority interrupt from being considered for a lower priority interrupt. The destination selection circuit attempts to determine a unique destination processor for each of the highest priority interrupt requests, such that these multiple interrupt requests can therefore be dispatched to different processors simultaneously. One or more of the interrupt requests may be "blocked" during a particular time period because all destination processors which could service the blocked requests are already processing other interrupts, performing higher priority tasks or are otherwise unavailable. These blocked interrupt requests are identified and the corresponding destination registers are masked such that the remaining non-blocked interrupt requests can be delivered to an available destination processor.
Inventors
- 👤 Hong-Chich Chou
- 👤 Jerng-Cherng Fan
- 👤 Won-Yih Lin
- 👤 Ching-Chin Huang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 10:25
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/24
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
160 words
A method of processing interrupt requests in a system having a plurality of processors, each of the interrupt requests having at least one destination processor associated therewith for servicing the interrupt request, the method comprising the steps of: masking those of the plurality of interrupt requests for which the destination processors associated therewith are unavailable at a given time, the step of masking including the steps of: applying a processor availability indicator for each of the plurality of processors to a destination mask circuit; utilizing the processor availability indicator to mask contents of destination registers associated with interrupt requests having an unavailable destination processor associated therewith as indicated by the processor availability indicators, and generating available interrupt destination indicators associated with each of the destination processors for each of the interrupt requests; and selecting from the remainder of the plurality of interrupt requests a particular interrupt to be delivered to an available destination processor associated with the particular interrupt request.
Claim 2
Independent Claim
160 words
A method of processing interrupt requests in a system having a plurality of processors, each of the interrupt requests having at least one destination processor associated therewith for servicing the interrupt request, the method comprising the steps of: masking those of the plurality of interrupt requests for which the destination processors associated therewith are unavailable at a given time, the step of masking including the steps of: applying a processor availability indicator for each of the plurality of processors to a destination mask circuit; utilizing the processor availability indicator to mask contents of destination registers associated with interrupt requests having an unavailable destination processor associated therewith as indicated by the processor availability indicators, and generating available interrupt destination indicators associated with each of the destination processors for each of the interrupt requests; and selecting from the remainder of the plurality of interrupt requests a particular interrupt to be delivered to an available destination processor associated with the particular interrupt request.
Claim 3
Dependent Claim
45 words
The method of claim 1 wherein the step of selecting from the remainder of the plurality of interrupts a particular interrupt to be delivered to an available destination register further includes the step of selecting a highest priority interrupt request from the remaining interrupt requests.
Claim 4
Dependent Claim
90 words
The method of claim 1 wherein the step of masking those of the plurality of interrupt requests for which the destination processors associated therewith are unavailable at a given time further includes the steps of: applying cpu task priority identifiers for each destination processor to a task priority mask circuit for the comparison of cpu task priority; applying said available interrupt destination indicators to the said task priority mask circuit; and generating masked interrupt destination signals indicative of the availability of the destination processors for each of the interrupt requests.
Claim 5
Independent Claim
159 words
A method of processing interrupt requests in a system having a plurality of processors each of the interrupt requests having at least one destination processor associated therewith for servicing the interrupt request the method comprising the steps of: masking those of the plurality of interrupt requests for which the destination processors associated therewith are unavailable at a given time, wherein the step of masking those of the plurality of interrupt requests for which the destination processors associated therewith are unavailable at a given time further includes the steps of: applying accepted interrupt request identifiers for each interrupt request accepted by the destination processors at a previous time to an acceptance mask circuit; and generating masked interrupt pending signals indicative of the interrupt requests that could be accepted by the destination processors; and selecting from the remainder of the plurality of interrupt requests a particular interrupt to be delivered to an available destination processor associated with the particular interrupt request.
Claim 6
Independent Claim
159 words
A method of processing interrupt requests in a system having a plurality of processors each of the interrupt requests having at least one destination processor associated therewith for servicing the interrupt request the method comprising the steps of: masking those of the plurality of interrupt requests for which the destination processors associated therewith are unavailable at a given time, wherein the step of masking those of the plurality of interrupt requests for which the destination processors associated therewith are unavailable at a given time further includes the steps of: applying accepted interrupt request identifiers for each interrupt request accepted by the destination processors at a previous time to an acceptance mask circuit; and generating masked interrupt pending signals indicative of the interrupt requests that could be accepted by the destination processors; and selecting from the remainder of the plurality of interrupt requests a particular interrupt to be delivered to an available destination processor associated with the particular interrupt request.
Claim 7
Independent Claim
211 words
A method of processing interrupt requests in a system having a plurality of processors, each of the interrupt requests having at least one destination processor associated therewith for servicing the interrupt request the method comprising the steps of: masking those of the plurality of interrupt requests for which the destination processors associated therewith are unavailable at a given time, wherein the step of masking those of the plurality of interrupt requests for which the destination processors associated therewith are unavailable at a given time further includes the steps of: masking contents of destination registers associated with interrupt requests having an unavailable destination processor associated therewith, as indicated by processor availability indicators, and as indicated by cpu task priority identifiers, and generating masked interrupt destination signals indicative of the availability of the destination processors for each of the interrupt requests, and masking contents of interrupt pending registers associated with interrupt requests having an unavailable destination processor associated therewith, as indicated by accepted interrupt request identifiers, and generating masked interrupt pending signals indicative of the interrupt requests that could be accepted by the destination processors; and selecting from the remainder of the plurality of interrupt requests a particular interrupt to be delivered to an available destination processor associated with the particular interrupt request.
Claim 8
Independent Claim
211 words
A method of processing interrupt requests in a system having a plurality of processors, each of the interrupt requests having at least one destination processor associated therewith for servicing the interrupt request the method comprising the steps of: masking those of the plurality of interrupt requests for which the destination processors associated therewith are unavailable at a given time, wherein the step of masking those of the plurality of interrupt requests for which the destination processors associated therewith are unavailable at a given time further includes the steps of: masking contents of destination registers associated with interrupt requests having an unavailable destination processor associated therewith, as indicated by processor availability indicators, and as indicated by cpu task priority identifiers, and generating masked interrupt destination signals indicative of the availability of the destination processors for each of the interrupt requests, and masking contents of interrupt pending registers associated with interrupt requests having an unavailable destination processor associated therewith, as indicated by accepted interrupt request identifiers, and generating masked interrupt pending signals indicative of the interrupt requests that could be accepted by the destination processors; and selecting from the remainder of the plurality of interrupt requests a particular interrupt to be delivered to an available destination processor associated with the particular interrupt request.
Claim 9
Dependent Claim
49 words
The method of claim 1 further including the step of determining whether to deliver a selected interrupt request to a particular destination processor based on a comparison of a priority of the selected interrupt request with a priority of another interrupt request currently being serviced by the destination processor.
Claim 10
Dependent Claim
113 words
The method of claim 6 wherein the step of determining whether to deliver a selected interrupt request to a particular destination processor further includes the steps of: storing the selected interrupt request and its corresponding priority in an interrupt request register associated with the destination processor; storing a priority of an interrupt request currently being serviced by the destination processor in an in-service register associated with the destination processor; comparing the priority of the selected interrupt request stored in the interrupt request register with the priority of the in-service interrupt request stored in the in-service register to determine whether or not the selected interrupt request should be delivered to the particular destination processor.
Claim 11
Dependent Claim
179 words
An interrupt controller for processing interrupt requests in a system having a plurality of processors, each of the interrupt requests having at least one destination processor associated therewith for servicing the interrupt request, the interrupt controller comprising: a mask circuit for masking those of the plurality of interrupt requests for which the destination processors associated therewith are unavailable at a given time, said mask circuit further includes a destination mask circuit which receives a processor availability indicator for each of the plurality of processors to a destination mask circuit, wherein the destination mask circuit utilizes the processor availability indicator to mask contents of destination registers associated with interrupt requests having an unavailable destination processor associated therewith, as indicated by the processor availability indicators, and generates available interrupt destination signals associated with each of the destination processors for each of the interrupt requests; and a priority comparison circuit and interrupt dispatch circuit for selecting from the remainder of the plurality of interrupt requests a particular interrupt to be delivered to an available destination processor associated with the particular interrupt request.
Claim 12
Dependent Claim
179 words
An interrupt controller for processing interrupt requests in a system having a plurality of processors, each of the interrupt requests having at least one destination processor associated therewith for servicing the interrupt request, the interrupt controller comprising: a mask circuit for masking those of the plurality of interrupt requests for which the destination processors associated therewith are unavailable at a given time, said mask circuit further includes a destination mask circuit which receives a processor availability indicator for each of the plurality of processors to a destination mask circuit, wherein the destination mask circuit utilizes the processor availability indicator to mask contents of destination registers associated with interrupt requests having an unavailable destination processor associated therewith, as indicated by the processor availability indicators, and generates available interrupt destination signals associated with each of the destination processors for each of the interrupt requests; and a priority comparison circuit and interrupt dispatch circuit for selecting from the remainder of the plurality of interrupt requests a particular interrupt to be delivered to an available destination processor associated with the particular interrupt request.
Claim 13
Dependent Claim
22 words
The interrupt controller of claim 8 wherein the priority comparison circuit selects a highest priority interrupt request from the remaining interrupt requests.
Claim 14
Dependent Claim
142 words
An interrupt controller for processing interrupt requests in a system having a plurality of processors, each of the interrupt requests having at least one destination processor associated therewith for servicing the interrupt request the interrupt controller comprising: a mask circuit for masking those of the plurality of interrupt requests for which the destination processors associated therewith are unavailable at a given time; a priority comparison circuit and interrupt dispatch circuit for selecting from the remainder of the plurality of interrupt requests a particular interrupt to be delivered to an available destination processor associated with the particular interrupt request; and an acceptance mask circuit which receives accepted interrupt request identifiers for each interrupt request accepted by the destination processors at a previous time, and generates a masked interrupt pending signal indicative of the interrupt requests that could be accepted by the destination processors.
Claim 15
Dependent Claim
142 words
An interrupt controller for processing interrupt requests in a system having a plurality of processors, each of the interrupt requests having at least one destination processor associated therewith for servicing the interrupt request the interrupt controller comprising: a mask circuit for masking those of the plurality of interrupt requests for which the destination processors associated therewith are unavailable at a given time; a priority comparison circuit and interrupt dispatch circuit for selecting from the remainder of the plurality of interrupt requests a particular interrupt to be delivered to an available destination processor associated with the particular interrupt request; and an acceptance mask circuit which receives accepted interrupt request identifiers for each interrupt request accepted by the destination processors at a previous time, and generates a masked interrupt pending signal indicative of the interrupt requests that could be accepted by the destination processors.
Claim 16
Dependent Claim
59 words
The interrupt controller of claim 8 wherein the mask circuit further includes: a task priority mask circuit for receiving the said available interrupt destination signals and cpu task priority identifiers associated with the destination processors, the task priority mask circuit generating masked interrupt destination signals indicative of the availability of the destination processors for each of the interrupt requests.
Claim 17
Dependent Claim
50 words
The interrupt controller of claim 8 wherein the priority comparison circuit determines whether to deliver a selected interrupt request to a particular destination processor based on a comparison of a priority of the selected interrupt request with a priority of another interrupt request currently being serviced by the destination processor.
Claim 18
Dependent Claim
102 words
The interrupt controller of claim 12 wherein the interrupt controller further includes: an interrupt request register associated with the destination processor for storing the selected interrupt request and its corresponding priority; an in-service register associated with the destination processor for storing a priority of an interrupt request currently being serviced by the destination processor; and a comparator for comparing the priority of the selected interrupt request stored in the interrupt request register with the priority of the in-service interrupt request stored in the in-service register to determine whether or not the selected interrupt request should be delivered to the particular destination processor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-05-17 | 2002-11-16 | 2003-05-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-05-17 | 2006-11-16 | 2007-05-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-05-17 | 2010-11-16 | 2011-05-18 | $7700.00 | Window Closed / Lapsed |