US5555430A
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US
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Interrupt control architecture for symmetrical multiprocessing system
Assignee: GlobalFoundries Inc
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Filing: 1994-05-31
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Granted: 1996-09-10
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Expires: 2014-05-31
Abstract
Abstract A symmetrical multiprocessing system is provided that includes centralized interrupt control unit. The interrupt control unit is coupled to a plurality of processing units and to a plurality of interrupt sources. The interrupt control unit advantageously allows for the expansion of each interrupt pin by setting the interrupt control unit in a cascade mode. Furthermore, the central control unit is responsive to specialized interrupt cycles which allows I/O devices and/or bus bridge devices to initiate of an interrupt without requiring a dedicated interrupt line. The central interrupt control unit further allows each interrupt to be prioritized independently of its associated vector ID, and prevents the occurrence of spurious interrupts by providing a programmable latency timer which causes the central interrupt control unit to delay its response to End Of Interrupt (EOI) instructions. An auto-chaining technique is further implemented by the central interrupt control unit to sequentially provide broadcast interrupts to various processing units based on their current task priority values. Finally, the central interrupt control unit further handles system management interrupts (SMIs) from sources such as power management units and ensures proper system operation even if the requested system management function affects operations being carried by other processing units.
Inventors
- 👤 Douglas Gephardt
- 👤 Rupaka Mahalingaiah
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 10:56
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/163; G06F15/17; G06F13/00; G06F13/14; G06F13/20; G06F13/24; G06F13/26
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
300 words
A multiprocessing system comprising: a plurality of processing units; a plurality of peripheral devices, wherein each of said peripheral devices is configured to generate a respective interrupt signal; and a central interrupt control unit coupled to said plurality of processing units and to said plurality of peripheral devices, wherein said central interrupt control unit is configured to receive said respective interrupt signals from said plurality of peripheral devices and is configured to provide corresponding processor interrupt signals to designated processing units, wherein said central interrupt control unit includes: a plurality of interrupt channels coupled to said plurality of peripheral devices, wherein each interrupt channel is configured to detect an assertion of an interrupt of a corresponding peripheral device, and wherein each interrupt channel further includes a programmable storage unit for storing a vector and a priority value associated with said interrupt of said corresponding peripheral device; a plurality of CPU channels coupled to said plurality of processing units, wherein each CPU channel is configured to receive interrupt information to control assertions of a corresponding processor interrupt, wherein said interrupt information includes said vector and priority value corresponding to each of several selected interrupts of said peripheral devices that have been asserted; and a central controller coupled to said plurality of interrupt channels and to said plurality of CPU channels, wherein said central controller is configured to route said interrupt information corresponding to said each of several interrupts that have been asserted from any of said plurality of interrupt channels to a designated CPU channel, and wherein said central controller is configured to prioritize several selected co-pending interrupts provided to said designated CPU channel in accordance with said priority values, whereby said designated processing unit is interrupted by a higher priority interrupt before being interrupted by a lower priority co-pending interrupt.
Claim 2
Dependent Claim
300 words
A multiprocessing system comprising: a plurality of processing units; a plurality of peripheral devices, wherein each of said peripheral devices is configured to generate a respective interrupt signal; and a central interrupt control unit coupled to said plurality of processing units and to said plurality of peripheral devices, wherein said central interrupt control unit is configured to receive said respective interrupt signals from said plurality of peripheral devices and is configured to provide corresponding processor interrupt signals to designated processing units, wherein said central interrupt control unit includes: a plurality of interrupt channels coupled to said plurality of peripheral devices, wherein each interrupt channel is configured to detect an assertion of an interrupt of a corresponding peripheral device, and wherein each interrupt channel further includes a programmable storage unit for storing a vector and a priority value associated with said interrupt of said corresponding peripheral device; a plurality of CPU channels coupled to said plurality of processing units, wherein each CPU channel is configured to receive interrupt information to control assertions of a corresponding processor interrupt, wherein said interrupt information includes said vector and priority value corresponding to each of several selected interrupts of said peripheral devices that have been asserted; and a central controller coupled to said plurality of interrupt channels and to said plurality of CPU channels, wherein said central controller is configured to route said interrupt information corresponding to said each of several interrupts that have been asserted from any of said plurality of interrupt channels to a designated CPU channel, and wherein said central controller is configured to prioritize several selected co-pending interrupts provided to said designated CPU channel in accordance with said priority values, whereby said designated processing unit is interrupted by a higher priority interrupt before being interrupted by a lower priority co-pending interrupt.
Claim 3
Dependent Claim
38 words
The multiprocessing system as recited in claim 1 wherein, upon assertion of a particular processor interrupt signal, a vector corresponding to said particular processor interrupt signal is provided to a processing unit receiving said particular processor interrupt signal.
Claim 4
Dependent Claim
42 words
The multiprocessing system as recited in claim 2 wherein said vector corresponding to said processor interrupt signal is indicative of which one of said plurality of peripheral devices that asserted a corresponding interrupt signal that caused assertion of said processor interrupt signal.
Claim 5
Dependent Claim
36 words
The multiprocessing system as recited in claim 2 wherein said vector corresponding to said processor interrupt signal is provided to said processing unit receiving said particular processor interrupt signal in response to an interrupt acknowledge cycle.
Claim 6
Dependent Claim
25 words
The multiprocessing system as recited in claim 4 wherein said interrupt acknowledge cycle is executed by said processing unit receiving said particular processor interrupt signal.
Claim 7
Dependent Claim
22 words
The multiprocessing system as recited in claim 1 wherein said central interrupt control unit is fabricated on a single integrated circuit die.
Claim 8
Dependent Claim
30 words
The multiprocessing system as recited in claim 1 wherein said vector associated with said interrupt of said corresponding peripheral device points to a starting address of an interrupt service routine.
Claim 9
Dependent Claim
26 words
The multiprocessing system as recited in claim 7 wherein said vector associated with said interrupt of said corresponding peripheral device is independent of said priority value.
Claim 10
Dependent Claim
342 words
A multiprocessing system comprising: a plurality of processing units; a plurality of peripheral devices, wherein each of said peripheral devices is configured to assert a respective interrupt signal when requiring servicing by a corresponding interrupt service routine; and a central interrupt control unit coupled to said plurality of processing units and to said plurality of peripheral devices, wherein said central interrupt control unit is fabricated on a single integrated integrated circuit die that includes: a plurality of interrupt channels coupled to said plurality of peripheral devices, wherein each interrupt channel is configured to detect an assertion of an interrupt of a corresponding peripheral device, and wherein each interrupt channel further includes a programmable storage unit for storing a vector, a destination and a priority value associated with said interrupt of said corresponding peripheral device, wherein said vector points to an address of an interrupt service routine designated for servicing said corresponding peripheral device, said destination indicates one of said processing units designated to execute said interrupt service routine, and said priority value indicates a priority of said interrupt of said corresponding peripheral device; a plurality of CPU channels each coupled to a respective processing unit, wherein each CPU channel is configured to receive interrupt information to control assertions of a corresponding processor interrupt, wherein said interrupt information includes said vector and priority value corresponding to each of several selected interrupts of said peripheral devices that have been asserted; and a central controller coupled to said plurality of interrupt channels and to said plurality of CPU channels, wherein said central controller is configured to route said interrupt information corresponding to said each of several interrupts that have been asserted from any of said plurality of interrupt channels to a designated CPU channel in accordance with said destination, and wherein said central controller is configured to prioritize several selected co-pending interrupts provided to said designated CPU channel in accordance with said priority values, whereby said designated processing unit is interrupted by a higher priority interrupt before being interrupted by a lower priority co-pending interrupt.
Claim 11
Dependent Claim
342 words
A multiprocessing system comprising: a plurality of processing units; a plurality of peripheral devices, wherein each of said peripheral devices is configured to assert a respective interrupt signal when requiring servicing by a corresponding interrupt service routine; and a central interrupt control unit coupled to said plurality of processing units and to said plurality of peripheral devices, wherein said central interrupt control unit is fabricated on a single integrated integrated circuit die that includes: a plurality of interrupt channels coupled to said plurality of peripheral devices, wherein each interrupt channel is configured to detect an assertion of an interrupt of a corresponding peripheral device, and wherein each interrupt channel further includes a programmable storage unit for storing a vector, a destination and a priority value associated with said interrupt of said corresponding peripheral device, wherein said vector points to an address of an interrupt service routine designated for servicing said corresponding peripheral device, said destination indicates one of said processing units designated to execute said interrupt service routine, and said priority value indicates a priority of said interrupt of said corresponding peripheral device; a plurality of CPU channels each coupled to a respective processing unit, wherein each CPU channel is configured to receive interrupt information to control assertions of a corresponding processor interrupt, wherein said interrupt information includes said vector and priority value corresponding to each of several selected interrupts of said peripheral devices that have been asserted; and a central controller coupled to said plurality of interrupt channels and to said plurality of CPU channels, wherein said central controller is configured to route said interrupt information corresponding to said each of several interrupts that have been asserted from any of said plurality of interrupt channels to a designated CPU channel in accordance with said destination, and wherein said central controller is configured to prioritize several selected co-pending interrupts provided to said designated CPU channel in accordance with said priority values, whereby said designated processing unit is interrupted by a higher priority interrupt before being interrupted by a lower priority co-pending interrupt.
Claim 12
Dependent Claim
38 words
The multiprocessing system as recited in claim 9 wherein, upon assertion of a particular processor interrupt signal, a vector corresponding to said particular processor interrupt signal is provided to a processing unit receiving said particular processor interrupt signal.
Claim 13
Dependent Claim
42 words
The multiprocessing system as recited in claim 10 wherein said vector corresponding to said processor interrupt signal is indicative of which one of said plurality of peripheral devices that asserted a corresponding interrupt signal that caused assertion of said processor interrupt signal.
Claim 14
Dependent Claim
36 words
The multiprocessing system as recited in claim 10 wherein said vector corresponding to said processor interrupt signal is provided to said processing unit receiving said particular processor interrupt signal in response to an interrupt acknowledge cycle.
Claim 15
Dependent Claim
25 words
The multiprocessing system as recited in claim 12 wherein said interrupt acknowledge cycle is executed by said processing unit receiving said particular processor interrupt signal.
Claim 16
Dependent Claim
30 words
The multiprocessing system as recited in claim 9 wherein said vector associated with said interrupt of said corresponding peripheral device points to a starting address of an interrupt service routine.
Claim 17
Dependent Claim
26 words
The multiprocessing system as recited in claim 14 wherein said vector associated with said interrupt of said corresponding peripheral device is independent of said priority value.
Claim 18
Dependent Claim
20 words
The multiprocessing system as recited in claim 9 wherein said programmable storage unit of each interrupt channel is software programmable.
Claim 19
Dependent Claim
225 words
A central interrupt control unit for a multiprocessing system including a plurality of processing units and a plurality of peripheral devices, said central interrupt control unit comprising: a plurality of interrupt channels, wherein each interrupt channel is configured to detect an assertion of an interrupt of a corresponding peripheral device, and wherein each interrupt channel further includes a programmable storage unit for storing a vector and a priority value associated with said interrupt of said corresponding peripheral device; a plurality of CPU channels, wherein each CPU channel is configured to receive interrupt information to control assertions of a corresponding processor interrupt, wherein said interrupt information includes said vector and priority value corresponding to each of several selected interrupts of said peripheral devices that have been asserted; and a central controller coupled to said plurality of interrupt channels and to said plurality of CPU channels, wherein said central controller is configured to route said interrupt information corresponding to said each of several interrupts that have been asserted from any of said plurality of interrupt channels to a designated CPU channel, and wherein said central controller is configured to prioritize several selected co-pending interrupts provided to said designated CPU channel in accordance with said priority values, whereby said designated processing unit is interrupted by a higher priority interrupt before being interrupted by a lower priority co-pending interrupt.
Claim 20
Dependent Claim
225 words
A central interrupt control unit for a multiprocessing system including a plurality of processing units and a plurality of peripheral devices, said central interrupt control unit comprising: a plurality of interrupt channels, wherein each interrupt channel is configured to detect an assertion of an interrupt of a corresponding peripheral device, and wherein each interrupt channel further includes a programmable storage unit for storing a vector and a priority value associated with said interrupt of said corresponding peripheral device; a plurality of CPU channels, wherein each CPU channel is configured to receive interrupt information to control assertions of a corresponding processor interrupt, wherein said interrupt information includes said vector and priority value corresponding to each of several selected interrupts of said peripheral devices that have been asserted; and a central controller coupled to said plurality of interrupt channels and to said plurality of CPU channels, wherein said central controller is configured to route said interrupt information corresponding to said each of several interrupts that have been asserted from any of said plurality of interrupt channels to a designated CPU channel, and wherein said central controller is configured to prioritize several selected co-pending interrupts provided to said designated CPU channel in accordance with said priority values, whereby said designated processing unit is interrupted by a higher priority interrupt before being interrupted by a lower priority co-pending interrupt.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-09-10 | 2000-03-11 | 2000-09-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-09-10 | 2004-03-11 | 2004-09-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-09-10 | 2008-03-11 | 2008-09-10 | $7700.00 | Window Closed / Lapsed |