Time of century counter synchronization using a SCI interconnect

Claim 2

A multiprocessor computer system having low skew time counters for synchronized processing events, the computer system comprising a plurality of nodes interconnected by a plurality of SCI rings, each node comprising: a time counter that generates a time value; a SCI controller that interfaces the node with a SCI ring; and a synchronization signal distribution path that conveys a synchronization signal between the SCI controller and the time counter; wherein one of the plurality of nodes is designated to be a master node, and the master node includes means for generating the synchronization signal, the signal is distributed to the remaining nodes of the system via the distribution path and SCI rings, and the signal changes the time value of each time counter in the system.

Claim 3

The computer system according to claim 1, wherein: the time counter is a time of century counter.

Claim 4

The computer system according to claim 1, wherein the means for generating the synchronization signal further comprises: a pulse synchronization generator that generates the signal, the signal is distributed to the time counter and the SCI controller on the master node through the distribution path; wherein the SCI controller receives the signal and locates an available data packet, the SCI controller sets a time counter synchronization bit in the data packet, and the data packet with the set bit is distributed to the remaining nodes of the system via the SCI rings.

Claim 5

The computer system according to claim 3, wherein: the time counter synchronization bit is in a header of the data packet.

Claim 6

The computer system according to claim 4, wherein the data packet is selected from the group consisting of: a send packet, an echo packet, and an idle packet.

Claim 7

The computer system according to claim 1, wherein each node further comprises: a clock that generates a clock frequency; wherein the time counter uses the clock frequency to generate the time value.

Claim 8

The computer system according to claim 6, wherein the frequency of the clock is 16 Mhz; and the means for generating the synchronization signal periodically generates the signal based upon the clock frequency.

Claim 9

The computer system according to claim 1, wherein each node further comprises: at least one processor for processing data; a memory for storing data; at least one processor agent for dispatching a request to transact with a target memory from the processor, and routing a response back to the processor, the at least one processor agent includes the time counter; at least one memory agent for controlling access to the memory, that receives the request from the processor agent and determines a location of the target memory; and at least one crossbar for routing the request and response between the processor agent and the memory agent; wherein when the memory agent determines the target memory is the memory, then the memory agent accesses the memory and responds to the processor; and when the memory agent determines the target memory is located on a remote node, then the memory agent forwards the request to the SCI controller, the SCI controller sends the request to the remote node through the SCI ring.

Claim 10

The computer system according to claim 8, wherein the means for generating the synchronization signal further comprises: a pulse synchronization generator that generates the signal, the signal is distributed to the processor agent and the SCI controller on the master node through the distribution path; wherein the SCI controller receives the signal and locates an available data packet, the SCI controller sets a time counter synchronization bit in the data packet, and the data packet with the set bit is distributed to the remaining nodes of the system via the SCI rings.

Claim 11

The computer system according to claim 9, wherein: the time counter synchronization bit is in a header of the data packet.

Claim 12

The computer system according to claim 9, wherein the data packet is selected from the group consisting of: a send packet, an echo packet, and an idle packet.

Claim 13

The computer system according to claim 8, wherein each node includes a means for generating the synchronization signal, each node further comprising: a master selector means for enabling only the means for generating the synchronization signal on the master node and disabling the means for generating the synchronization signal on the remaining nodes.

Claim 14

The computer system according to claim 8, wherein: each node comprises eight processor agents with eight time counters; each node comprises sixteen processors; each node comprises eight SCI controllers; and and each processor agent is coupled to two processors.

Claim 15

The computer system according to claim 13, wherein: one of the processor agents in the master node is designated the master processor agent; one of the SCI controllers in the master node is designated the master SCI controller; the means for generating the synchronization signal resides in the master processing agent; the synchronization signal distribution path conveys the synchronization signal between all SCI controllers and all time counters on each node; the master processing agent distributes the signal to the remaining processing agents in the master node via the distribution path, and the signal changes the time value of each time counter in the master node; the master SCI controller distributed the signal to the remaining nodes of the system via the SCI rings; and the SCI controllers of the remaining nodes receive the signal and distribute the signal to the processing agents in the remaining nodes via the distribution paths in each of the remaining nodes, and the signal changes the time value of each time counter in each of the remaining nodes.

Claim 16

The computer system according to claim 1, wherein: the plurality of nodes are arranged as a two dimensional array with at least one respective SCI ring connecting each node in a respective row of the array, and at least one respective SCI ring connecting each node in a respective column of the array.

Claim 17

The computer system according to claim 15, wherein: each node comprises eight SCI controllers, such that the array has eight SCI rings connecting the nodes in each of the rows, and eight SCI rings connecting the nodes in each of the columns.

Claim 18

A multiprocessor computer system in combination with a SCI data packet; the computer system comprises a plurality of nodes including a master node, that are interconnected by a plurality of SCI rings; the master node comprises a time counter that generates a time value, a SCI controller that interfaces the node with a SCI ring, and synchronization signal distribution path that conveys a synchronization signal between the SCI controller and the time counter; the data packet comprising: a header that includes a time counter synchronization bit and data symbols; wherein the master node includes means for generating synchronization signal that periodically sets the time counter synchronization bit in the data packet, and the data packet with the set bit serves as the synchronization signal that is distributed to the remaining nodes of the system via the distribution wire and SCI rings, and the signal changes the time value of each time counter in the system.

Claim 19

A multiprocessor computer system in combination with a SCI data packet; the computer system comprises a plurality of nodes including a master node, that are interconnected by a plurality of SCI rings; the master node comprises a time counter that generates a time value, a SCI controller that interfaces the node with a SCI ring, and synchronization signal distribution path that conveys a synchronization signal between the SCI controller and the time counter; the data packet comprising: a header that includes a time counter synchronization bit and data symbols; wherein the master node includes means for generating synchronization signal that periodically sets the time counter synchronization bit in the data packet, and the data packet with the set bit serves as the synchronization signal that is distributed to the remaining nodes of the system via the distribution wire and SCI rings, and the signal changes the time value of each time counter in the system.

Claim 20

The combination multiprocessor computer system and SCI data packet according to claim 17, wherein the data packet is selected from the group consisting of: a send packet, an echo packet, and an idle packet.

Claim 21

The combination multiprocessor computer system and SCI data packet according to claim 17, wherein: the time counter is a time of century counter.

Claim 24

The method of claim 20, in which the data pathway is a scalable coherent interface network.

Claim 25

The method of claim 20, in which the temporal relationship is synchronicity.

Claim 26

The method of claim 20, in which the timing event is a synchronization pulse.

Claim 27

The method of claim 20, in which the master time counter is a time of century counter.

Claim 28

The method of claim 20, in which the remote time counters are time of century counters.

Claim 29

The method of claim 20, in which the master time counter is on a master node, and second selected ones of the remote time counters are on other nodes.

Claim 30

The method of claim 20, in which the data packet is selected from a group consisting of a send packet, an echo packet, and an idle packet.

Claim 33

The method of claim 28, in which the data pathway is a scalable coherent interface network.

Claim 34

The method of claim 28, in which the master time counter is a time of century counter.

Claim 35

The method of claim 28, in which the remote time counters are time of century counters.

Claim 36

The method of claim 28, in which the data packet is selected from a group consisting of a send packet, an echo packet, and an idle packet.