Patent US5904530A successfully refreshed from Google Patents.
US5904530A
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US
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Method of making LDD structure spaced from channel doped region
Assignee: MagnaChip Semiconductor Ltd
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Filing: 1997-06-12
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Granted: 1999-05-18
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Expires: 2017-06-12
Abstract
Abstract A MOSFET and method of manufacture thereof is disclosed in which an ion implantation layer formed in the channel region is isolated from the source and drain regions. The source and drain regions are of a lightly doped drain or "LDD" structure. According to this MOSFET and method, short channel effects are decreased by the channel implant, yet hot carrier and doping compensation effects are decreased, junction capacitance is decreased, and mobility of the carriers also may be improved.
Inventors
- 👤 Hyung Soon Shin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 04:18
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0225; H10D30/60; H10D30/601; H10D30/0227; H10D62/00; H10D62/10; H10D62/17; H10D62/213; H10D62/221; H10D62/235; H10D62/299; H10D62/307; H10D64/00; H10D64/01; H10D64/018; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0147; H10P; H10P30/00; H10P30/20; H10P30/222; H10D30/0217
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
239 words
A method for manufacturing a MOSFET on a substrate of a first conductivity type, comprising the steps of: forming an implant mask having an opening to the substrate, wherein the opening defines a doped region to be formed in a channel region of the substrate; implanting ions of the first conductivity type into the substrate through the opening for forming the doped region of the first conductivity type in the channel region of the substrate, wherein at least a portion of the doped region is positioned in the channel region; forming a gate insulating layer on the substrate, wherein at least a portion of the gate insulating layer is positioned over the channel region; forming a gate electrode on the gate insulating layer, wherein at least a portion of the gate electrode is positioned over the channel region, wherein the gate electrode is formed subsequent to the implant for forming the doped region; forming a source region of a second conductivity type in the substrate with a first ion implantation into the substrate, wherein the doped region in the channel region is spaced apart from the source region; and forming a drain region of the second conductivity in the substrate with the first ion implantation, wherein the channel region is defined in the substrate between at least portions of the source and drain regions, wherein the doped region in the channel region is spaced apart from the drain region.
Claim 2
Independent Claim
239 words
A method for manufacturing a MOSFET on a substrate of a first conductivity type, comprising the steps of: forming an implant mask having an opening to the substrate, wherein the opening defines a doped region to be formed in a channel region of the substrate; implanting ions of the first conductivity type into the substrate through the opening for forming the doped region of the first conductivity type in the channel region of the substrate, wherein at least a portion of the doped region is positioned in the channel region; forming a gate insulating layer on the substrate, wherein at least a portion of the gate insulating layer is positioned over the channel region; forming a gate electrode on the gate insulating layer, wherein at least a portion of the gate electrode is positioned over the channel region, wherein the gate electrode is formed subsequent to the implant for forming the doped region; forming a source region of a second conductivity type in the substrate with a first ion implantation into the substrate, wherein the doped region in the channel region is spaced apart from the source region; and forming a drain region of the second conductivity in the substrate with the first ion implantation, wherein the channel region is defined in the substrate between at least portions of the source and drain regions, wherein the doped region in the channel region is spaced apart from the drain region.
Claim 3
Dependent Claim
19 words
The method of claim 1, wherein the first conductivity type is p-type and the second conductivity type is n-type.
Claim 4
Dependent Claim
19 words
The method of claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type.
Claim 5
Dependent Claim
37 words
The method of claim 1, wherein the opening includes a sidewall along side portions of the opening, wherein the doped region formed in the channel region is formed by ion implantation through the opening including the sidewall.
Claim 6
Dependent Claim
13 words
The method of claim 1, wherein the gate insulating layer comprises silicon dioxide.
Claim 7
Dependent Claim
34 words
The method of claim 1, further comprising the step of forming a side insulating layer substantially above the substrate along the sides of the gate electrode, wherein the side insulating layers comprise silicon dioxide.
Claim 8
Dependent Claim
11 words
The method of claim 1, wherein the gate electrode comprises polysilicon.
Claim 9
Dependent Claim
26 words
The method of claim 1, further comprising the step of forming a side insulating layer substantially above the substrate along the sides of the gate electrode.
Claim 10
Dependent Claim
39 words
The method of claim 8, wherein the side insulating layer serves as an ion implantation barrier to present the ions from being implanted in portions of the source and drain regions that are directly adjacent to the channel region.
Claim 11
Dependent Claim
53 words
The method of claim 1, wherein the drain region is of a lightly doped drain structure, wherein the concentration of the second conductivity type is lower in the portions of the drain region directly adjacent to the channel region than in portions of the drain region that are removed from the channel region.
Claim 12
Dependent Claim
66 words
The method of claim 1, wherein the source and drain regions each are of a lightly doped drain structure, wherein the concentrations of the second conductivity type in the source and drain regions are lower in the portions of the source and drain regions directly adjacent to the channel region than in portions of the source and drain regions that are removed from the channel region.
Claim 13
Independent Claim
262 words
A method of manufacturing a semiconductor device on a substrate of a first conductivity type, comprising the steps of: forming an implant barrier layer on a surface of the substrate; patterning the implant barrier layer to form an opening to the substrate; forming a first side wall insulating layer on sides of the opening; implanting ions of the first conductivity type into the substrate through the opening, wherein the ions of the first conductivity type substantially are implanted into the substrate except beneath the first side wall insulating layer and the implant barrier layer, wherein the implant forms a doped region in the substrate defined by the opening and the first side wall insulating layer; removing the first side wall insulating layer; forming a gate insulating layer on the substrate in the openings of the implant barrier layer; forming a gate layer on the gate insulating layer, wherein the gate layer is formed subsequent to the implant for forming the dope region; removing the implant barrier layer; implanting ions of a second conductivity type into the substrate, wherein the ions of the second conductivity type, substantially are implanted into the substrate except beneath the gate layer and are spaced apart from the doped region; forming a second side wall insulating layer on the sides of the gate layer; and implanting ions of the second conductivity type into the substrate, wherein the ions of the second conductivity type substantially are implanted into the substrate except beneath the gate layer and the second sidewall insulating layer and are spaced apart from the doped region.
Claim 14
Independent Claim
262 words
A method of manufacturing a semiconductor device on a substrate of a first conductivity type, comprising the steps of: forming an implant barrier layer on a surface of the substrate; patterning the implant barrier layer to form an opening to the substrate; forming a first side wall insulating layer on sides of the opening; implanting ions of the first conductivity type into the substrate through the opening, wherein the ions of the first conductivity type substantially are implanted into the substrate except beneath the first side wall insulating layer and the implant barrier layer, wherein the implant forms a doped region in the substrate defined by the opening and the first side wall insulating layer; removing the first side wall insulating layer; forming a gate insulating layer on the substrate in the openings of the implant barrier layer; forming a gate layer on the gate insulating layer, wherein the gate layer is formed subsequent to the implant for forming the dope region; removing the implant barrier layer; implanting ions of a second conductivity type into the substrate, wherein the ions of the second conductivity type, substantially are implanted into the substrate except beneath the gate layer and are spaced apart from the doped region; forming a second side wall insulating layer on the sides of the gate layer; and implanting ions of the second conductivity type into the substrate, wherein the ions of the second conductivity type substantially are implanted into the substrate except beneath the gate layer and the second sidewall insulating layer and are spaced apart from the doped region.
Claim 15
Dependent Claim
46 words
The method of claim 12, wherein the step of forming the first side wall insulating layer comprises the steps of: depositing insulating material over the surface of the substrate within the opening; and etching back the insulating material to form the first side wall insulating layer.
Claim 16
Dependent Claim
12 words
The method of claim 12, wherein the implant barrier layer comprises nitride.
Claim 17
Dependent Claim
22 words
The method of claim 12, wherein the gate layer comprises polysilicon and the first and second side wall insulating layers comprise oxide.
Claim 18
Dependent Claim
47 words
The method of claim 1, wherein the doped region is spaced apart from the source region and the drain region by a region of the substrate that is of the first conductivity type and has a doped concentration less than a doping concentration of the doped region.
Claim 19
Dependent Claim
53 words
The method of claim 12, wherein the doped region is spaced apart from regions where the ions of the second conductivity type are implanted by a region of the substrate that is of the first conductivity type and has a doping concentration that is less than a doping concentration of the doped region.
Claim 20
Independent Claim
235 words
A method of manufacturing an MOSFET on a substrate of a first conductivity type, comprising the steps of: forming an implant barrier layer on the substrate; patterning the implant barrier layer to form an opening to the substrate; forming a first side wall insulating layer on sides of the opening in the implant barrier layer; implanting ions of the first conductivity type into the substrate through the opening, wherein the first side wall insulating layer and the barrier layer serve as an implant mask, wherein the implant forms a doped region in the substrate; removing the first side wall insulating layer; forming a gate insulating layer on the substrate in the opening of the implant barrier layer; forming a gate layer on the gate insulating layer, wherein the gate layer is formed subsequent to the implant for forming the doped region; removing the implant barrier layer; implanting ions of a second conductivity type into the substrate except a portion beneath the gate layer, wherein the implanted ions are spaced apart from the doped region; forming a second side wall insulating layer at sides of the gate layer; and implanting ions of the second conductivity type into the substrate, wherein the ions of the second conductivity type substantially are implanted into the substrate except beneath the gate layer and the second side wall insulating layer, wherein the implanted ions are spaced apart from the doped region.
Claim 21
Independent Claim
235 words
A method of manufacturing an MOSFET on a substrate of a first conductivity type, comprising the steps of: forming an implant barrier layer on the substrate; patterning the implant barrier layer to form an opening to the substrate; forming a first side wall insulating layer on sides of the opening in the implant barrier layer; implanting ions of the first conductivity type into the substrate through the opening, wherein the first side wall insulating layer and the barrier layer serve as an implant mask, wherein the implant forms a doped region in the substrate; removing the first side wall insulating layer; forming a gate insulating layer on the substrate in the opening of the implant barrier layer; forming a gate layer on the gate insulating layer, wherein the gate layer is formed subsequent to the implant for forming the doped region; removing the implant barrier layer; implanting ions of a second conductivity type into the substrate except a portion beneath the gate layer, wherein the implanted ions are spaced apart from the doped region; forming a second side wall insulating layer at sides of the gate layer; and implanting ions of the second conductivity type into the substrate, wherein the ions of the second conductivity type substantially are implanted into the substrate except beneath the gate layer and the second side wall insulating layer, wherein the implanted ions are spaced apart from the doped region.
Claim 22
Dependent Claim
19 words
The method of claim 18, wherein the gate insulating layer comprises silicon dioxide and the gate layer comprises polysilicon.
Claim 23
Dependent Claim
12 words
The method of claim 18, wherein the implant barrier layer comprises nitride.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-05-17 | 2002-11-16 | 2003-05-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-05-17 | 2006-11-16 | 2007-05-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-05-17 | 2010-11-16 | 2011-05-18 | $7700.00 | Window Closed / Lapsed |