Patent US5903759A successfully refreshed from Google Patents.
US5903759A
Expired / Lapsed
US
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Software performance analysis using hardware analyzer
Assignee: HP Inc
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Filing: 1997-06-04
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Granted: 1999-05-11
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Expires: 2017-06-04
Abstract
Abstract The present invention provides a method and an apparatus for analyzing the performance of a computer program inn a way that is accurate in light of prefetching caching operations. The method operates by inserting output sequences into a computer program. An output sequence is a sequence of instructions which cause the program to send an output through the data bus to an output terminal. A hardware analyzer records the output from the output terminal, and this output is used to calculate performance of the computer program. The present invention provides facilities to insert output sequences into executable code, thereby allowing performance analysis to take place without time consuming recompilation. The present invention requires only a small number connections from a hardware analyzer to output terminals connected to the processor data bus. This greatly simplifies the process of gathering data with a hardware analyzer. The present invention also provides for sending information to the output terminals in a format that indicates the progress of the program through subroutine and function calls.
Inventors
- 👤 Tsyr-Shya Joe Sun
- 👤 Dar-Ren Leu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 22:59
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/30; G06F11/34; G06F11/3466; G06F8/00; G06F8/40; G06F8/41; G06F8/44; G06F8/443; G06F8/4434; G06F8/4436
Claims Analysis
Total Claims: 47
Claim 1
Independent Claim
117 words
A method for analyzing performance of a computer code, the method operating in a computer system including, a processor, a memory, an output terminal, an address bus, and a data bus coupled to the processor, the memory and the output terminal, the method comprising the steps of: inserting at least one output sequence into the computer code, the output sequence including a plurality of instructions which cause the processor to send an output through the data bus to the output terminal; connecting a hardware analyzer to the output terminal; running the computer code without recompilation; monitoring the output terminal with the hardware analyzer to gather data; and calculating from the data a performance of the computer code.
Claim 2
Independent Claim
117 words
A method for analyzing performance of a computer code, the method operating in a computer system including, a processor, a memory, an output terminal, an address bus, and a data bus coupled to the processor, the memory and the output terminal, the method comprising the steps of: inserting at least one output sequence into the computer code, the output sequence including a plurality of instructions which cause the processor to send an output through the data bus to the output terminal; connecting a hardware analyzer to the output terminal; running the computer code without recompilation; monitoring the output terminal with the hardware analyzer to gather data; and calculating from the data a performance of the computer code.
Claim 3
Dependent Claim
35 words
The method of claim 1, wherein the step of inserting at least one output sequence into the computer code includes replacing an original instruction in the computer code with the at least one output sequence.
Claim 4
Dependent Claim
36 words
The method of claim 1, wherein in the step of inserting at least one output sequence into the computer code, the at least one output sequence can be inserted at any instruction in the computer code.
Claim 5
Dependent Claim
39 words
The method of claim 1, wherein in the step of inserting at least one output sequence into the computer code, the at least one output sequence is located at entry and exit points of functions in the computer code.
Claim 6
Dependent Claim
28 words
The method of claim 1, wherein the step of inserting at least one output sequence into the computer code is performed by a debugger program in the memory.
Claim 7
Dependent Claim
19 words
The method of claim 1, wherein the step of running the computer code is performed by an in-circuit emulator.
Claim 8
Dependent Claim
55 words
The method of claim 1, including the step of receiving user input into the computer system from a computer user, and wherein the step of inserting the at least one output sequence into the computer code uses the user input to determine where to insert the at least one output sequence into the computer code.
Claim 9
Dependent Claim
32 words
The method of claim 1, wherein the computer code is in executable form, and the step of inserting inserts the at least one output sequence into the computer code in executable form.
Claim 10
Dependent Claim
61 words
The method of claim 1, wherein: the computer code is in executable form; and in the step of inserting the at least one output sequence into the computer code, the inserting replaces an original instruction in the computer code with an output sequence which causes the processor to send an output to the output terminal and to execute the original instruction.
Claim 11
Dependent Claim
130 words
The method of claim 1, wherein: the computer code is in executable form; and in the step of inserting the at least one output sequence into the computer code, the inserting replaces an original instruction in the computer code with a part of an output sequence in the at least one output sequence, the output sequence including, a first jump instruction to jump to an outside location outside of the computer code, a copy of the original instruction at the outside location to perform the functions of the original instruction, an output instruction at the outside location, which causes the processor to send an output to the output terminal, and a second jump instruction at the outside location to jump back to a location immediately following the first jump instruction.
Claim 12
Dependent Claim
15 words
The method of claim 1, wherein the output terminal includes a plurality of output terminals.
Claim 13
Dependent Claim
15 words
The method of claim 1, wherein the output terminal includes fewer than eight output terminals.
Claim 14
Dependent Claim
15 words
The method of claim 1, wherein the output terminal connects directly to the data bus.
Claim 15
Dependent Claim
22 words
The method of claim 1, wherein the output terminal includes an unused output pin of a register coupled to the data bus.
Claim 16
Dependent Claim
22 words
The method of claim 1, wherein the output terminal is coupled to the data bus and the address bus through combinatorial logic.
Claim 17
Dependent Claim
19 words
The method of claim 1, wherein the output terminal is used only for purposes of performance analysis and debugging.
Claim 18
Dependent Claim
16 words
The method of claim 1, wherein the data gathered by the hardware analyzer includes timing information.
Claim 19
Dependent Claim
34 words
The method of claim 1, wherein the output sent through the data bus to the output terminal includes information on the progress of the processor through subroutine and functions calls in the computer code.
Claim 20
Independent Claim
177 words
A method for analyzing performance of a computer code, the method operating in a computer system including, a processor, a memory, an output terminal, an address bus, and a data bus coupled to the processor, the memory and the output terminal, the method comprising the steps of: inserting output sequences into the computer code, the output sequences including a plurality of instructions which cause the processor to send outputs through the data bus to the output terminal, wherein the output terminal is coupled to the data bus through a selector, the outputs including outputs regarding entry and exit of functions in the computer code; connecting a hardware analyzer to the output terminal; running the computer code; monitoring the output terminal with the hardware analyzer to gather data; and calculating from the data a performance of the computer code; wherein: the computer code is in source code form; the step of inserting inserts the output sequences into the computer code in source code form; and the method includes the step of compiling the computer code into executable form.
Claim 21
Independent Claim
177 words
A method for analyzing performance of a computer code, the method operating in a computer system including, a processor, a memory, an output terminal, an address bus, and a data bus coupled to the processor, the memory and the output terminal, the method comprising the steps of: inserting output sequences into the computer code, the output sequences including a plurality of instructions which cause the processor to send outputs through the data bus to the output terminal, wherein the output terminal is coupled to the data bus through a selector, the outputs including outputs regarding entry and exit of functions in the computer code; connecting a hardware analyzer to the output terminal; running the computer code; monitoring the output terminal with the hardware analyzer to gather data; and calculating from the data a performance of the computer code; wherein: the computer code is in source code form; the step of inserting inserts the output sequences into the computer code in source code form; and the method includes the step of compiling the computer code into executable form.
Claim 22
Independent Claim
167 words
A method for analyzing performance of a computer code, the method operating in a computer system including, a processor, a memory, an output terminal, an address bus, and a data bus coupled to the processor, the memory and the output terminal, the method comprising the steps of: inserting at least one output sequence into the computer code by replacing an original instruction in the computer code with the at least one output sequence, the output sequence including a plurality of instructions which cause the processor to send an output through the data bus to the output terminal; receiving user input into the computer system from a computer user, the user input being used to determine where to insert the at least one output sequence into the computer code, connecting a hardware analyzer to the output terminal; running the computer code without recompilation; monitoring the output terminal with the hardware analyzer to gather data including timing information; and calculating from the data a performance of the computer code.
Claim 23
Independent Claim
167 words
A method for analyzing performance of a computer code, the method operating in a computer system including, a processor, a memory, an output terminal, an address bus, and a data bus coupled to the processor, the memory and the output terminal, the method comprising the steps of: inserting at least one output sequence into the computer code by replacing an original instruction in the computer code with the at least one output sequence, the output sequence including a plurality of instructions which cause the processor to send an output through the data bus to the output terminal; receiving user input into the computer system from a computer user, the user input being used to determine where to insert the at least one output sequence into the computer code, connecting a hardware analyzer to the output terminal; running the computer code without recompilation; monitoring the output terminal with the hardware analyzer to gather data including timing information; and calculating from the data a performance of the computer code.
Claim 24
Independent Claim
114 words
An apparatus for measuring performance of a computer code, comprising: a processor; a memory; an output terminal positioned and shaped to receive a connection to a hardware analyzer; and a data bus coupled to the processor, the memory and the output terminal; wherein the memory includes resources that insert at least one output sequence into the computer code, the output sequence including a plurality of instructions which cause the processor to send an output through the data bus to the output terminal; wherein the resources that insert at least one output sequence into the computer code include resources that replace an original instruction in the computer code with the at least one output sequence.
Claim 25
Independent Claim
114 words
An apparatus for measuring performance of a computer code, comprising: a processor; a memory; an output terminal positioned and shaped to receive a connection to a hardware analyzer; and a data bus coupled to the processor, the memory and the output terminal; wherein the memory includes resources that insert at least one output sequence into the computer code, the output sequence including a plurality of instructions which cause the processor to send an output through the data bus to the output terminal; wherein the resources that insert at least one output sequence into the computer code include resources that replace an original instruction in the computer code with the at least one output sequence.
Claim 26
Dependent Claim
15 words
The apparatus of claim 21, wherein the memory includes a semiconductor memory and disk drive.
Claim 27
Dependent Claim
39 words
The apparatus of claim 21, wherein the resources that insert at least one output sequence into the computer code include resources which allow the at least one output sequence to be inserted at any instruction in the computer code.
Claim 28
Dependent Claim
41 words
The apparatus of claim 21, wherein the resources that insert the at least one output sequence into the computer code include resources to locate the at least one output sequence at entry and exit points of functions in the computer code.
Claim 29
Dependent Claim
28 words
The apparatus of claim 21, wherein the resources that insert the at least one output sequence into the computer code are within a debugger program in the memory.
Claim 30
Dependent Claim
25 words
The apparatus of claim 21, wherein the resources that insert the at least one output sequence into the computer code are within an in-circuit emulator.
Claim 31
Dependent Claim
58 words
The apparatus of claim 21, including a user interface for receiving input into the computer system from a computer user, and wherein the resources that insert the at least one output sequence into the computer code include resources which use the user input to determine where to insert the at least one output sequence into the computer code.
Claim 32
Dependent Claim
45 words
The apparatus of claim 21, wherein the computer code is in executable form, and the resources that insert the at least one output sequence into the computer code include resources to insert the at least one output sequence into the computer code in executable form.
Claim 33
Dependent Claim
60 words
The apparatus of claim 21, wherein: the computer code is in executable form; and the resources that insert the at least one output sequence into the computer code include resources that replace an original instruction in the computer code with an output sequence which causes the processor to send output to the output terminal and to execute the original instruction.
Claim 34
Dependent Claim
127 words
The apparatus of claim 21, wherein: the computer code is in executable form; and the resources that insert the at least one output sequence into the computer code include resources to replace an original instruction in the computer code with an output sequence in the at least one output sequence, the output sequence including, a first jump instruction to jump to an outside location outside of the computer code, a copy of the original instruction at the outside location to perform the functions of the original instruction, an output instruction at the outside location, which causes the processor to send an output to the output terminal, and a second jump instruction at the outside location to jump back to a location immediately following the first jump instruction.
Claim 35
Dependent Claim
15 words
The apparatus of claim 21, wherein the output terminal includes a plurality of output terminals.
Claim 36
Dependent Claim
15 words
The apparatus of claim 21, wherein the output terminal includes fewer than eight output terminals.
Claim 37
Dependent Claim
14 words
The apparatus of claim 21, wherein the output terminal connects directly the data bus.
Claim 38
Dependent Claim
25 words
The apparatus of claim 21, wherein the output terminal includes an output pin of an unused bit in a register coupled to the data bus.
Claim 39
Dependent Claim
22 words
The apparatus of claim 21, wherein the output terminal is coupled to the data bus and the address bus through combinatorial logic.
Claim 40
Dependent Claim
19 words
The apparatus of claim 21, wherein the output terminal is used only for purposes of performance analysis and debugging.
Claim 41
Dependent Claim
34 words
The method of claim 21, wherein the output sent through the data bus to the output terminal includes information on the progress of the processor through subroutine and functions calls in the computer code.
Claim 42
Independent Claim
148 words
An apparatus for measuring performance of a computer code, comprising: a processor; a memory; an output terminal positioned and shaped to receive a connection to a hardware analyzer; and a data bus coupled to the processor, the memory and the output terminal, wherein the output terminal is coupled to the data bus through a selector; wherein the memory includes resources that insert output sequences into the computer code, the output sequence including a plurality of instructions which cause the processor to send outputs through the data bus to the output terminal, the outputs including outputs regarding entry and exit of functions in the computer code; wherein: the computer code is in the source form; the resources that insert the output sequences into the computer code insert the output sequences into the computer code in source code form; and including resources that compile the computer code into executable form.
Claim 43
Independent Claim
148 words
An apparatus for measuring performance of a computer code, comprising: a processor; a memory; an output terminal positioned and shaped to receive a connection to a hardware analyzer; and a data bus coupled to the processor, the memory and the output terminal, wherein the output terminal is coupled to the data bus through a selector; wherein the memory includes resources that insert output sequences into the computer code, the output sequence including a plurality of instructions which cause the processor to send outputs through the data bus to the output terminal, the outputs including outputs regarding entry and exit of functions in the computer code; wherein: the computer code is in the source form; the resources that insert the output sequences into the computer code insert the output sequences into the computer code in source code form; and including resources that compile the computer code into executable form.
Claim 44
Independent Claim
97 words
An apparatus for measuring performance of a computer code, comprising: a processor: a memory; a data bus coupled to the processor and the memory; an output terminal coupled to the data bus, the output terminal positioned and shaped to receive a connection from a hardware analyzer; an address decoder; an address bus coupled to the, address decoder; and a selector coupled to the data bus, the decoder and the output terminal, the selector establishing a signal path between the data bus and the output terminal when the address decoder detects a desired address on the address bus.
Claim 45
Independent Claim
97 words
An apparatus for measuring performance of a computer code, comprising: a processor: a memory; a data bus coupled to the processor and the memory; an output terminal coupled to the data bus, the output terminal positioned and shaped to receive a connection from a hardware analyzer; an address decoder; an address bus coupled to the, address decoder; and a selector coupled to the data bus, the decoder and the output terminal, the selector establishing a signal path between the data bus and the output terminal when the address decoder detects a desired address on the address bus.
Claim 46
Independent Claim
145 words
A method for analyzing performance of a computer code, the method operating in a computer system including, a processor, a memory, an output terminal, an address bus, and a data bus coupled to the processor, the memory and the output terminal, the method comprising the steps of: inserting at least one output sequence into the computer code, the output sequence including a plurality of instructions which cause the processor to send an output through the data bus to the output terminal; connecting a hardware analyzer to the output terminal; running the computer code; monitoring the output terminal with the hardware analyzer to gather data; and calculating from the data a performance of the computer code; wherein the step of inserting at least one output sequence into the computer code includes replacing an original instruction in the computer code with the at least one output sequence.
Claim 47
Independent Claim
145 words
A method for analyzing performance of a computer code, the method operating in a computer system including, a processor, a memory, an output terminal, an address bus, and a data bus coupled to the processor, the memory and the output terminal, the method comprising the steps of: inserting at least one output sequence into the computer code, the output sequence including a plurality of instructions which cause the processor to send an output through the data bus to the output terminal; connecting a hardware analyzer to the output terminal; running the computer code; monitoring the output terminal with the hardware analyzer to gather data; and calculating from the data a performance of the computer code; wherein the step of inserting at least one output sequence into the computer code includes replacing an original instruction in the computer code with the at least one output sequence.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-05-10 | 2002-11-09 | 2003-05-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-05-10 | 2006-11-09 | 2007-05-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-05-10 | 2010-11-09 | 2011-05-11 | $7700.00 | Window Closed / Lapsed |