Patent US1646728A successfully refreshed from Google Patents.
Patent US5903601A successfully refreshed from Google Patents.
US5903601A
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Power reduction for UART applications in standby mode
Assignee: Texas Instruments Inc
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Filing: 1996-12-17
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Granted: 1999-05-11
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Expires: 2016-12-17
Abstract
Abstract A power reduction system for a UART system having a controllable oscillator for producing free-running clock signals. A controlled clock synchronizer having an output terminal is coupled to the oscillator and responsive to both a first control signal thereto and application of the free-running clock signals thereto to provide synchronized pulses and is responsive to both a second control signal different from the first control signal thereto and application of the free-running clock signals thereto to cease production of the synchronized pulses at the output terminal. A UART core controls the oscillator and the clock synchronizer and is operated under control of clock signals from the clock synchronizer. The controllable oscillator includes an inverter having a feedback circuit thereacross including a switch responsive to the third control signal to cause the oscillator to cease oscillation. The synchronizer includes a bistable circuit responsive to the first and second control signals and a gate responsive to the bistable circuit and the clock signals for controlling the status of the synchronized pulses at the output terminal.
Inventors
- 👤 Khodor S. Elnashar
- 👤 Mahmoud M. Yazdani
- 👤 Clarence D. Lewis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 19:16
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3234; G06F1/3237; G06F1/325; G06F13/00; G06F13/38; G06F13/382; G06F13/385; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
114 words
A power reduction system for a UART system, which comprises: (a) a controlled oscillator for producing free-running clock signals; (b) a controlled clock synchronizer having an output terminal, said clock synchronizer coupled to said oscillator and responsive to both a first control signal thereto and application of said free-running clock signals thereto to provide synchronized pulses and responsive to both a second control signal thereto different from said first control signal thereto and application of said free-running clock signals thereto to cease production of said synchronized pulses at said output terminal; and (c) a UART core controlling said oscillator and said clock synchronizer and operational under control of clock signals from said clock synchronizer.
Claim 2
Dependent Claim
114 words
A power reduction system for a UART system, which comprises: (a) a controlled oscillator for producing free-running clock signals; (b) a controlled clock synchronizer having an output terminal, said clock synchronizer coupled to said oscillator and responsive to both a first control signal thereto and application of said free-running clock signals thereto to provide synchronized pulses and responsive to both a second control signal thereto different from said first control signal thereto and application of said free-running clock signals thereto to cease production of said synchronized pulses at said output terminal; and (c) a UART core controlling said oscillator and said clock synchronizer and operational under control of clock signals from said clock synchronizer.
Claim 3
Dependent Claim
28 words
The system of claim 1 wherein said controllable oscillator includes circuitry responsive to a third control signal from said UART core to cause said oscillator to cease oscillation.
Claim 4
Dependent Claim
32 words
The system of claim 2 wherein said oscillator includes an inverter having a feedback circuit thereacross and said circuitry responsive to a third control signal is a switch in said feedback circuit.
Claim 5
Dependent Claim
44 words
The system of claim 3 wherein said synchronizer includes a bistable circuit responsive to said first and second control signals and a gate responsive to said bistable circuit and said clock signals for controlling the status of said synchronized pulses at said output terminal.
Claim 6
Dependent Claim
12 words
The system of claim 4 wherein said gate is an AND gate.
Claim 7
Dependent Claim
38 words
The system of claim 9 wherein said bistable circuit is a first flip flop having an output and a second flip flop responsive to said output of said first flip flop to provide an input to said gate.
Claim 8
Dependent Claim
38 words
The system of claim 4 wherein said bistable circuit is a first flip flop having an output and a second flip flop responsive to said output of said first flip flop to provide an input to said gate.
Claim 9
Dependent Claim
44 words
The system of claim 2 wherein said synchronizer includes a bistable circuit responsive to said first and second control signals and a gate responsive to said bistable circuit and said clock signals for controlling the status of said synchronized pulses at said output terminal.
Claim 10
Dependent Claim
12 words
The system of claim 8 wherein said gate is an AND gate.
Claim 11
Dependent Claim
38 words
The system of claim 9 wherein said bistable circuit is a first flip flop having an output and a second flip flop responsive to said output of said first flip flop to provide an input to said gate.
Claim 12
Dependent Claim
38 words
The system of claim 8 wherein said bistable circuit is a first flip flop having an output and a second flip flop responsive to said output of said first flip flop to provide an input to said gate.
Claim 13
Dependent Claim
44 words
The system of claim 1 wherein said synchronizer includes a bistable circuit responsive to said first and second control signals and a gate responsive to said bistable circuit and said clock signals for controlling the status of said synchronized pulses at said output terminal.
Claim 14
Dependent Claim
12 words
The system of claim 12 wherein said gate is an AND gate.
Claim 15
Dependent Claim
38 words
The system of claim 13 wherein said bistable circuit is a first flip flop having an output and a second flip flop responsive to said output of said first flip flop to provide an input to said gate.
Claim 16
Dependent Claim
38 words
The system of claim 12 wherein said bistable circuit is a first flip flop having an output and a second flip flop responsive to said output of said first flip flop to provide an input to said gate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-05-10 | 2002-11-09 | 2003-05-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-05-10 | 2006-11-09 | 2007-05-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-05-10 | 2010-11-09 | 2011-05-11 | $7700.00 | Window Closed / Lapsed |