US5568100A
Expired / Lapsed
US
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Synchronous power down clock oscillator device
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1995-09-22
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Granted: 1996-10-22
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Expires: 2015-09-22
Abstract
Abstract This invention provides a synchronous, power down oscillating device that provides only uniform pulses having no glitches at its output. The circuit is able to provide a synchronous output for two low power stand-by modes of a battery powered device. The circuit includes an oscillator that sends an oscillator signal to a synchronizing chain of D flip-flops. Input to the flip-flops is provided through an OR gate. The output of the flip-flops is logically ORed with the oscillator signal. The resultant output from the circuit is always a synchronized signal.
Inventors
- 👤 Bart N. Locanthi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:45
CPC Classifications
H; H03; H03L; H03L3/00; H03K; H03K3/00; H03K3/01; H03K3/013; H03K3/02; H03K3/027; H03K3/037; H03K3/0375; H03K5/00; H03K5/13
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
48 words
A clock oscillator device, comprising: an oscillator for generating an oscillator signal; and an clock output controller for generating a uniform clock signal using the oscillator signal, an OFF signal and a HALT signal, the uniform clock signal comprising one of a non-oscillating signal and an oscillating signal.
Claim 2
Dependent Claim
48 words
A clock oscillator device, comprising: an oscillator for generating an oscillator signal; and an clock output controller for generating a uniform clock signal using the oscillator signal, an OFF signal and a HALT signal, the uniform clock signal comprising one of a non-oscillating signal and an oscillating signal.
Claim 3
Dependent Claim
37 words
The clock oscillator device of claim 1, further comprising a delay circuit, the delay circuit generating a delay signal based on the OFF signal ensuring that the oscillator is stable before the uniform clock signal is generated.
Claim 4
Dependent Claim
76 words
The clock oscillator device of claim 1, wherein the oscillator output controller comprises: a signal synchronizer; input logic circuitry; and output logic circuitry, wherein the input logic circuitry generates a DISABLE signal based on the HALT signal and the DELAY signal, the signal synchronizer generates a synchronizing signal by synchronizing the DISABLE signal with the oscillator signal and the output logic circuitry generates the uniform clock signal based on the synchronizing signal and the oscillator signal.
Claim 5
Dependent Claim
25 words
The clock oscillator device of claim 3, wherein the signal synchronizer comprises at least one D-flip-flop, wherein the at least one D-flip-flop is serially connected.
Claim 6
Dependent Claim
31 words
The clock oscillator device of claim 3, wherein the input logic circuitry comprises an OR gate for logically ORing the halt signal and the DELAY signal and outputting the DISABLE signal.
Claim 7
Dependent Claim
32 words
The clock oscillator device of claim 3, wherein the output logic circuitry comprises an OR gate for ORing the synchronizing signal and the oscillator signal and for outputting the uniform clock signal.
Claim 8
Dependent Claim
17 words
The clock oscillator device of claim 3, wherein a power on reset circuit pre-sets the signal synchronizer.
Claim 9
Dependent Claim
19 words
The clock oscillator device of claim 1, wherein an oscillator controller receives the OFF signal and controls the oscillator.
Claim 10
Independent Claim
47 words
A method for generating a uniform clock signal, comprising: generating an oscillator signal; generating the uniform clock signal based on the oscillator signal, a HALT signal and an OFF signal, wherein the uniform clock signal is comprised of one of a non-oscillating signal and an oscillating signal.
Claim 11
Independent Claim
47 words
A method for generating a uniform clock signal, comprising: generating an oscillator signal; generating the uniform clock signal based on the oscillator signal, a HALT signal and an OFF signal, wherein the uniform clock signal is comprised of one of a non-oscillating signal and an oscillating signal.
Claim 12
Dependent Claim
22 words
The method of claim 9, wherein generating the uniform clock signal further comprises generating a DELAY signal by delaying the OFF signal.
Claim 13
Dependent Claim
48 words
The method of claim 10, further comprising: generating a DISABLE signal based on the HALT signal and the DELAY signal; synchronizing the DISABLE signal with the oscillator signal thereby generating a synchronizing signal; and generating the uniform clock signal based on the synchronizing signal and the oscillator signal.
Claim 14
Dependent Claim
21 words
The method of claim 11, wherein the DISABLE signal is generated by logically ORing the HALT signal and the DELAY signal.
Claim 15
Dependent Claim
66 words
The method of claim 11, wherein synchronizing comprises: serially connecting at least one D-flip-flop; inputting the DISABLE signal into a D input of a first one of the serially connected at least one D-flip-flop; connecting the oscillator signal to clock inputs of the at least one D-flip-flop; and generating the synchronizing signal by outputting a last Q output of the serially connected at least one D-flip-flop.
Claim 16
Dependent Claim
26 words
The method of claim 13, wherein synchronizing further comprises setting the at least one D flip-flop to a logical "1" prior to generating the synchronizing signal.
Claim 17
Dependent Claim
22 words
The method of claim 11, wherein the uniform clock signal is generated by logically ORing the synchronizing signal and the oscillator signal.
Claim 18
Dependent Claim
14 words
The method of claim 9, further comprising controlling the oscillator with an oscillator controller.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-10-22 | 2000-04-22 | 2000-10-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-10-22 | 2004-04-22 | 2004-10-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-10-22 | 2008-04-22 | 2008-10-22 | $7700.00 | Window Closed / Lapsed |