US5903044A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Hermetic chip and method of manufacture
Assignee: Micron Technology Inc
•
Filing: 1997-08-13
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Granted: 1999-05-11
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Expires: 2017-08-13
Abstract
Abstract A fully hermetically sealed semiconductor chip and its method of manufacture. The semiconductor chip of the present invention is fully hermetically sealed on both sides and the edges thereof through the use of suitable coatings applied thereto, such as glass, to prevent an environmental attack of the semiconductor chip. The fully hermetically sealed semiconductor chip of the present invention does not require the use of a separate package for the hermetic sealing of the chip, thereby reducing the size of such a chip. The method of the manufacture of the semiconductor chip of the present invention provides a simple process for the fully hermetic sealing of both sides and the edges of the semicondutor chip without the use of a separate package.
Inventors
- 👤 Warren M. Farnworth
- 👤 Salman Akram
- 👤 Alan G. Wood
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 18:39
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/01; H10W72/019; H10W74/00; H10W74/01; H10W74/10; H10W74/111; H10W74/40; H10W74/43; H10W70/00; H10W70/60; H10W72/50; H10W72/531; H10W72/536; H10W72/59; H10W72/90; H10W72/931; H10W72/934; H10W72/951; H10W90/00; H10W90/701; H10W90/751; H10W90/754; H10W90/756; Y; Y10; Y10S; Y10S438/00; Y10S438/958; Y10S438/959
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
405 words
A semiconductor wafer having a plurality of semiconductor devices formed thereon, said wafer comprising: a semiconductor wafer substrate having a first side, a second side, a peripheral edge, a thickness, and a plurality of street areas thereon forming areas on the semiconductor wafer substrate within which semiconductor devices are located, the semiconductor wafer substrate having portions thereof removed through the thickness thereof in the plurality of street areas thereof; a plurality of semiconductor devices formed on the first side of the semiconductor wafer substrate, each semiconductor device separated from an adjacent semiconductor device by a street area extending therefrom over a portion of the semiconductor wafer substrate, each semiconductor device having a plurality of bond pads formed thereon, each semiconductor device formed on the semiconductor wafer substrate being separated from an adjacent semiconductor device by the portions of the substrate removed from the street areas of the semiconductor wafer substrate, each semiconductor device having a plurality of peripheral edges formed by the portions of the semiconductor wafer substrate removed in the plurality of street areas; a first coating covering the first side of the semiconductor wafer substrate and the plurality of semiconductor devices formed on the first side of the semiconductor wafer substrate sealingly engaging the first side of the semiconductor wafer substrate, the first coating on the first side of the semiconductor wafer substrate covering the plurality of semiconductor devices formed thereon except for the plurality of bond pads formed on each semiconductor device; a second coating covering the second side of the semiconductor wafer substrate, substantially filling the portions of the street areas of the semiconductor wafer substrate which have been removed thereby separating areas of the semiconductor wafer substrate from other areas thereof and contacting the first coating in the portions of the street areas of the semiconductor wafer substrate which have been removed, the second coating substantially hermetically sealingly engaging the plurality of peripheral edges of each semiconductor device; and at least one metal circuit being connected to at least one bond pad of the plurality of bond pads of each semiconductor device and extending to a location adjacent one of the plurality of peripheral edges of at least one semiconductor device of the plurality of semiconductor devices, the at least one metal circuit sealingly engaging the first coating on the semiconductor wafer substrate and the at least one bond pad of the plurality of bond pads of each semiconductor device.
Claim 2
Dependent Claim
405 words
A semiconductor wafer having a plurality of semiconductor devices formed thereon, said wafer comprising: a semiconductor wafer substrate having a first side, a second side, a peripheral edge, a thickness, and a plurality of street areas thereon forming areas on the semiconductor wafer substrate within which semiconductor devices are located, the semiconductor wafer substrate having portions thereof removed through the thickness thereof in the plurality of street areas thereof; a plurality of semiconductor devices formed on the first side of the semiconductor wafer substrate, each semiconductor device separated from an adjacent semiconductor device by a street area extending therefrom over a portion of the semiconductor wafer substrate, each semiconductor device having a plurality of bond pads formed thereon, each semiconductor device formed on the semiconductor wafer substrate being separated from an adjacent semiconductor device by the portions of the substrate removed from the street areas of the semiconductor wafer substrate, each semiconductor device having a plurality of peripheral edges formed by the portions of the semiconductor wafer substrate removed in the plurality of street areas; a first coating covering the first side of the semiconductor wafer substrate and the plurality of semiconductor devices formed on the first side of the semiconductor wafer substrate sealingly engaging the first side of the semiconductor wafer substrate, the first coating on the first side of the semiconductor wafer substrate covering the plurality of semiconductor devices formed thereon except for the plurality of bond pads formed on each semiconductor device; a second coating covering the second side of the semiconductor wafer substrate, substantially filling the portions of the street areas of the semiconductor wafer substrate which have been removed thereby separating areas of the semiconductor wafer substrate from other areas thereof and contacting the first coating in the portions of the street areas of the semiconductor wafer substrate which have been removed, the second coating substantially hermetically sealingly engaging the plurality of peripheral edges of each semiconductor device; and at least one metal circuit being connected to at least one bond pad of the plurality of bond pads of each semiconductor device and extending to a location adjacent one of the plurality of peripheral edges of at least one semiconductor device of the plurality of semiconductor devices, the at least one metal circuit sealingly engaging the first coating on the semiconductor wafer substrate and the at least one bond pad of the plurality of bond pads of each semiconductor device.
Claim 3
Dependent Claim
14 words
The semiconductor wafer of claim 1, wherein: the first coating comprises a glass coating.
Claim 4
Dependent Claim
14 words
The semiconductor wafer of claim 1, wherein: the second coating comprises a glass coating.
Claim 5
Dependent Claim
27 words
The semiconductor wafer of claim 1, further comprising: a plurality of metal circuits located on the first coating on the first side of the semiconductor wafer substrate.
Claim 6
Dependent Claim
175 words
A hermetically sealed semiconductor chip comprising: a semiconductor chip having a first surface, a second surface, a plurality of lateral edges therearound, and at least one bond pad located on the first surface; a coating of a first material substantially covering the first surface except for the at least one bond pad, the second surface, and the plurality of lateral edges wherein the semiconductor chip is substantially sealed, the coating of the first material including one material from a group of materials including a glass material and a ceramic material; and a second coating covering the at least one bond pad located on the first surface of the semiconductor chip, the second coating sealingly engaging the first coating and sealingly engaging the at least one bond pad, the second coating including an electrically conductive material to electrically connect the second coating to the at least one bond pad, the second coating extending from the at least one bond pad to at least one lateral edge of the plurality of lateral edges of the semiconductor chip.
Claim 7
Dependent Claim
175 words
A hermetically sealed semiconductor chip comprising: a semiconductor chip having a first surface, a second surface, a plurality of lateral edges therearound, and at least one bond pad located on the first surface; a coating of a first material substantially covering the first surface except for the at least one bond pad, the second surface, and the plurality of lateral edges wherein the semiconductor chip is substantially sealed, the coating of the first material including one material from a group of materials including a glass material and a ceramic material; and a second coating covering the at least one bond pad located on the first surface of the semiconductor chip, the second coating sealingly engaging the first coating and sealingly engaging the at least one bond pad, the second coating including an electrically conductive material to electrically connect the second coating to the at least one bond pad, the second coating extending from the at least one bond pad to at least one lateral edge of the plurality of lateral edges of the semiconductor chip.
Claim 8
Dependent Claim
16 words
The hermetically sealed semiconductor chip of claim 5, wherein the second coating comprises: a metal coating.
Claim 9
Independent Claim
246 words
A method of making sealed semiconductor chips, said method comprising the steps of: forming at least one semiconductor device on a first side of a wafer substrate having the first side, a second side, and a thickness, the at least one semiconductor device having a plurality of sides and at least one bond pad thereon; thinning the thickness of the wafer substrate from the second side thereof; coating the first side of the wafer substrate with a first coating to substantially seal the at least one semiconductor device formed on the first side of the wafer substrate; removing a portion of the wafer substrate from each side of the at least one semiconductor device formed on the first side of the wafer substrate extending from the second side of the wafer substrate to the coating on the first side of the wafer substrate; coating the second side of the wafer substrate with a second coating to substantially seal the second side of the wafer substrate and to substantially seal the plurality of sides of the at least one semiconductor device; removing a portion of the first coating on the first side of the wafer substrate to uncover a portion of the at least one bond pad located on the at least one semiconductor device; and applying a third coating to the at least one bond pad of the at least one semiconductor device to sealingly engage the at least one bond pad and the first coating.
Claim 10
Independent Claim
246 words
A method of making sealed semiconductor chips, said method comprising the steps of: forming at least one semiconductor device on a first side of a wafer substrate having the first side, a second side, and a thickness, the at least one semiconductor device having a plurality of sides and at least one bond pad thereon; thinning the thickness of the wafer substrate from the second side thereof; coating the first side of the wafer substrate with a first coating to substantially seal the at least one semiconductor device formed on the first side of the wafer substrate; removing a portion of the wafer substrate from each side of the at least one semiconductor device formed on the first side of the wafer substrate extending from the second side of the wafer substrate to the coating on the first side of the wafer substrate; coating the second side of the wafer substrate with a second coating to substantially seal the second side of the wafer substrate and to substantially seal the plurality of sides of the at least one semiconductor device; removing a portion of the first coating on the first side of the wafer substrate to uncover a portion of the at least one bond pad located on the at least one semiconductor device; and applying a third coating to the at least one bond pad of the at least one semiconductor device to sealingly engage the at least one bond pad and the first coating.
Claim 11
Dependent Claim
36 words
The method of claim 7, further comprising the step of: removing a portion of the third coating applied to the first coating adjacent the at least one bond pad of the at least one semiconductor device.
Claim 12
Dependent Claim
21 words
The method of claim 7, further comprising the step of: separating the at least one semiconductor device from the wafer substrate.
Claim 13
Dependent Claim
57 words
The method of claim 7, further comprising the step of: separating the at least one semiconductor device from the wafer substrate by removing a portion of the second coating substantially extending into the portion of the wafer substrate removed from each side of the at least one semiconductor device and removing a portion of the first coating.
Claim 14
Independent Claim
132 words
A method of making a sealed semiconductor device, said method comprising the steps of: forming a plurality of semiconductor devices on a first side of a wafer substrate having the first side, a second side, and a thickness, each semiconductor device having a plurality of sides and a plurality of bond pads thereon; coating the first side of the wafer substrate with a first coating to substantially seal the plurality of semiconductor devices formed on the first side of the wafer substrate; thinning the thickness of the wafer substrate from the second side thereof; removing a portion of the wafer substrate from each side of the plurality of sides of each semiconductor device formed on the wafer substrate extending through the thickness thereof; and coating the second side of the wafer substrate.
Claim 15
Independent Claim
132 words
A method of making a sealed semiconductor device, said method comprising the steps of: forming a plurality of semiconductor devices on a first side of a wafer substrate having the first side, a second side, and a thickness, each semiconductor device having a plurality of sides and a plurality of bond pads thereon; coating the first side of the wafer substrate with a first coating to substantially seal the plurality of semiconductor devices formed on the first side of the wafer substrate; thinning the thickness of the wafer substrate from the second side thereof; removing a portion of the wafer substrate from each side of the plurality of sides of each semiconductor device formed on the wafer substrate extending through the thickness thereof; and coating the second side of the wafer substrate.
Claim 16
Dependent Claim
13 words
The method of claim 11, wherein the second coating comprises a resist coating.
Claim 17
Dependent Claim
84 words
The method of claim 12, wherein the step of removing a portion of the wafer substrate includes etching the wafer substrate from each side of the plurality of sides of each semiconductor device formed on the wafer substrate, the portion of the wafer substrate removed from each side of the plurality of sides of each semiconductor device substantially extending from the second side of the wafer substrate to substantially the first coating on the first side of the wafer substrate through the thickness thereof.
Claim 18
Dependent Claim
24 words
The method of claim 13, further comprising the step of: removing the second coating of resist from the second side of the wafer substrate.
Claim 19
Dependent Claim
22 words
The method of claim 13, further comprising the step of: applying a third coating to the second side of the wafer substrate.
Claim 20
Dependent Claim
14 words
The method of claim 15, wherein the third coating is a coating of glass.
Claim 21
Dependent Claim
24 words
The method of claim 15, further comprising the step of: applying a fourth coating of resist to the first side of the wafer substrate.
Claim 22
Dependent Claim
30 words
The method of claim 17, further comprising the step of: etching substantially the first coating on the first side of the wafer substrate in selected areas of the wafer substrate.
Claim 23
Dependent Claim
39 words
The method of claim 18, further comprising the step of: removing the fourth coating of resist on the first side of the wafer substrate after the etching of the first coating on the first side of the wafer substrate.
Claim 24
Dependent Claim
22 words
The method of claim 10, further comprising the step of: applying a fifth coating to the first side of the wafer substrate.
Claim 25
Dependent Claim
13 words
The method of claim 20, wherein the fifth coating comprises a metal coating.
Claim 26
Dependent Claim
22 words
The method of claim 20, further comprising the step of: applying a sixth coating to the first side of the wafer substrate.
Claim 27
Dependent Claim
12 words
The method of claim 22, wherein the sixth coating is a resist.
Claim 28
Dependent Claim
46 words
The method of claim 22, further comprising the step of: etching portions of the fifth coating on the first side of the wafer substrate thereby leaving portions of the fifth coating on the first side of the wafer substrate in predetermined areas of the wafer substrate.
Claim 29
Dependent Claim
39 words
The method of claim 24, further comprising the step of: removing substantially the sixth coating from the first side of the wafer substrate thereby uncovering predetermined portions of the fifth coating on the first side of the wafer substrate.
Claim 30
Dependent Claim
17 words
The method of claim 25, further comprising the step of: dividing the wafer substrate into semiconductor devices.
Claim 31
Dependent Claim
20 words
The method of claim 25, wherein the step of dividing the wafer substrate comprises: sawing the wafer into semiconductor devices.
References Cited (Backward Citations)
US5014159A
Cited
US4866571A
Cited
US4821151A
Cited
US4756977A
Cited
US4749631B1
Cited
US4749631A
Cited
US4769345A
Cited
US4967260A
Cited
US5128737A
Cited
US5323051A
Cited
US5455459A
Cited
US5481135A
Cited
US5547906A
Cited
US5336928A
Cited
US5497033A
Cited
US5635766A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-05-10 | 2002-11-09 | 2003-05-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-05-10 | 2006-11-09 | 2007-05-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-05-10 | 2010-11-09 | 2011-05-11 | $7700.00 | Window Closed / Lapsed |