Hermetically sealed semiconductor device

Claim 2

A semiconductor device which includes a semiconductor body comprising a section of a semiconductor wafer defined by dicing lines which divide said semiconductor wafer into a plurality of semiconductor bodies, said semiconductor body having circuit metallization carried by one or more insulating layers for connection to active regions of said device, and an oxide layer having inner edges defining windows overlying said circuit metallization to expose bonding pad areas of said metallization for connection to said active regions, said oxide layer having outer edges remote from said bonding pad areas, the improvement comprising a metal layer of a metal which acts as a barrier against migration of corrosion resistant metal formed on and covering said bonding pad areas, said outer edges of said insulating and oxide layers being spaced inwardly of said dicing lines, a protective layer extending over said outer edges of said insulating and oxide layers and in contact with the semiconductor body between said outer edges and said dicing lines to seal said outer edges of said insulating and oxide layers and environmentally protect said device, said protective layer having inner edges defining windows at said bonding pad areas, and a corrosion resistant metal layer formed on said metal layer for connecting to said bonding pad areas through said metal layer, said corrosion resistant metal layer extending over and sealing said inner edges of said protective layer.

Claim 3

A semiconductor device as in claim 1 in which the corrosion resistant metal layer is gold.

Claim 4

A semiconductor device as in claim 1 in which said semiconductor body has an upper surface, a lower surface and side surfaces extending between said upper and lower surfaces, said semiconductor device including a bottom protective layer, said protective layer extending over said side surfaces of said semiconductor body to merge with the bottom protective layer to cocoon said device.

Claim 5

A semiconductor device as in claim 2 in which said metal layer, protective layer and gold layer are multiple layers to provide pinhole coverage and in which at least one of the gold layers extends over said inner edges of at least one of the protective layers.

Claim 6

A semiconductor device as in claim 1 in which said protective layer comprises a metal protective layer and a silicon oxide layer and in which said corrosion resistant metal layer extends over said inner edges of at least one of the metal protective layer and the silicon oxide layer.

Claim 7

A semiconductor device which includes a semiconductor body comprising a section of a semiconductor wafer defined by dicing lines which divide said semiconductor wafer into a plurality of semiconductor bodies, said semiconductor body having circuit metallization carried by one or more insulating layers for connection to active regions of said device, and an oxide layer having inner edges defining windows overlying said circuit metallization to expose bond pad areas of said metallization for connection to said active regions, said oxide layer and said insulating layers having outer edges remote from said bond pad areas, the improvement comprising aluminum bond pads on said metallization at said bond pad areas, a layer of a metal which acts as a barrier against migration of gold formed on and covering said aluminum bond pads, said outer edges of said insulating and oxide layers being spaced inwardly of said dicing lines, a protective layer having inner edges defining windows at said bond pad areas, said protective layer extending over said outer edges of said insulating and oxide layers and contacting the semiconductor body between said outer edges and said dicing lines to seal said outer edges of said insulating and oxide layers and environmentally protect said device, sealing means for sealing said inner edges of said oxide layer to environmentally protect said device, and a gold layer formed on said metal layer for connecting to said aluminum bond pads through said metal layer, said gold layer extending over said sealing means for sealing said metal layer.

Claim 8

A semiconductor device which includes a semiconductor body comprising a section of a semiconductor wafer defined by dicing lines which divide said semiconductor wafer into a plurality of semiconductor bodies, said semiconductor body having circuit metallization carried by one or more insulating layers for connection to active regions of said device, and an oxide layer having inner edges defining windows overlying said circuit metallization to expose bond pad areas of said metallization for connection to said active regions, said oxide layer and said insulating layers having outer edges remote from said bond pad areas, the improvement comprising aluminum bond pads on said metallization at said bond pad areas, a layer of a metal which acts as a barrier against migration of gold formed on and covering said aluminum bond pads, said outer edges of said insulating and oxide layers being spaced inwardly of said dicing lines, a protective layer having inner edges defining windows at said bond pad areas, said protective layer extending over said outer edges of said insulating and oxide layers and contacting the semiconductor body between said outer edges and said dicing lines to seal said outer edges of said insulating and oxide layers and environmentally protect said device, sealing means for sealing said inner edges of said oxide layer to environmentally protect said device, and a gold layer formed on said metal layer for connecting to said aluminum bond pads through said metal layer, said gold layer extending over said sealing means for sealing said metal layer.

Claim 9

A semiconductor device as in claim 6 in which said semiconductor body has upper and lower surfaces and side surfaces extending between said upper and lower surfaces, said semiconductor body including a bottom protective layer, said protective layer extending over said side surfaces of said semiconductor body to merge with said bottom protective layer to cocoon the device.

Claim 10

A semiconductor device as in claim 6 in which said metal layer, protective layer and gold layer are multiple layers to provide pinhole coverage and in which at least one of the gold layers extends over said inner edges of at least one of the protective layers.

Claim 11

A semiconductor device as in claim 6 in which said protective layer comprises a metal protective layer and a silicon oxide layer and in which said gold layer extends over said inner edges of at least one of the metal protective layer and the silicon oxide layer.

Claim 12

A semiconductor device as in claim 9 in which said semiconductor body has upper and lower surfaces and side surfaces extending between said upper and lower surfaces, and further including a bottom protective layer, said metal protective layer and silicon oxide layer extending over said side surfaces of said semiconductor body to merge with the bottom protective layer.

Claim 13

A semiconductor device as in claim 9 in which said metal layer metal protective layer, gold layer and silicon oxide layer comprise multiple layers to provide pinhole coverage and in which at least one of the gold layers extends over said inner edges of at least one of the metal protective layer and silicon oxide layers.

Claim 14

A semiconductor device which includes a semiconductor body comprising a section of a semiconductor wafer defined by dicing lines which divide said semiconductor wafer into a plurality of semiconductor bodies, said semiconductor body having circuit metallization carried by one or more insulating layers for connection to active regions of said device, and an oxide layer having inner edges defining windows overlying said circuit metallization to expose bond pad areas of said metallization for connection to said active regions, said oxide layer and said insulating layers having outer edges remote from said bond pad areas, the improvement comprising a first metal layer of a metal which acts as a barrier against migration of gold formed on and covering said bond pad areas, said outer edges of said insulating and oxide layers being spaced inwardly of said dicing lines, a protective layer extending over said outer edges of said insulating and oxide layers and in contact with the semiconductor body between said outer edges and said dicing lines to seal said outer edges of said insulating and oxide layers and environmentally protect said device, said protective layer having inner edges defining windows at said bond pad areas, a gold layer formed on said first metal layer for connecting to said bond pad areas through said first metal layer, said gold layer extending over and sealing said inner edges of said protective layer, a second metal layer which acts as a barrier against migration of solder covering said gold layer, and a solder bond pad formed on said second metal layer.

Claim 15

A semiconductor device which includes a semiconductor body comprising a section of a semiconductor wafer defined by dicing lines which divide said semiconductor wafer into a plurality of semiconductor bodies, said semiconductor body having circuit metallization carried by one or more insulating layers for connection to active regions of said device, and an oxide layer having inner edges defining windows overlying said circuit metallization to expose bond pad areas of said metallization for connection to said active regions, said oxide layer and said insulating layers having outer edges remote from said bond pad areas, the improvement comprising a first metal layer of a metal which acts as a barrier against migration of gold formed on and covering said bond pad areas, said outer edges of said insulating and oxide layers being spaced inwardly of said dicing lines, a protective layer extending over said outer edges of said insulating and oxide layers and in contact with the semiconductor body between said outer edges and said dicing lines to seal said outer edges of said insulating and oxide layers and environmentally protect said device, said protective layer having inner edges defining windows at said bond pad areas, a gold layer formed on said first metal layer for connecting to said bond pad areas through said first metal layer, said gold layer extending over and sealing said inner edges of said protective layer, a second metal layer which acts as a barrier against migration of solder covering said gold layer, and a solder bond pad formed on said second metal layer.

Claim 16

A semiconductor device as in claim 12 in which said semiconductor body has upper and lower surfaces and side surfaces extending between said upper and lower surfaces, said semiconductor device including a bottom protective layer, said protective layer extending over said side surfaces of said semiconductor body to merge with said bottom protective layer to cocoon the device.

Claim 17

A semiconductor device as in claim 12 in which said first metal layer, protective layer and gold layer are multiple layers to provide pinhole coverage and in which at least one of the gold layers extends over said inner edges of at least one of the protective layers.

Claim 18

A semiconductor device as in claim 12 in which said protective layer comprises a metal protective layer and a silicon oxide layer and in which said gold layer extends over said inner edges of at least one of the protective metal layer and the silicon oxide layer.

Claim 19

A semiconductor device as in claim 15 in which said semiconductor body includes upper and lower surfaces and side surfaces extending between said upper and lower surfaces, and further including a bottom protective layer, said metal protective layer and silicon oxide layer extending over said side surfaces of said semiconductor body to merge with the bottom protective layer.

Claim 20

A semiconductor device as in claim 15 in which said first and second metal layers, metal protective layer, gold layer and silicon oxide layer comprise multiple layers to provide pinhole coverage and in which at least one of the gold layers extends over said inner edges of at least one of the metal protective layers and silicon oxide layers.

Claim 21

A semiconductor device as in claim 1 in which said metal layer extends over said inner edges of said oxide layer and said protective layer is an insulating layer.

Claim 22

A semiconductor device as in claim 1 in which said metal layer extends over said inner edges of said oxide layer and said protective layer is a silicon oxide layer.

Claim 23

A semiconductor device as in claim 1 in which said protective layer is a metal layer.

Claim 24

A semiconductor device as in claim 20 in which said semiconductor body includes upper and lower surfaces and side surfaces extending between said upper and lower surfaces, and further including a bottom protective layer, said metal protective layer and silicon oxide layer extending over said side surfaces of said semiconductor body to merge with the bottom protective layer.

Claim 25

A semiconductor device as in claim 20 in which said metal layer, metal protective layer, corrosion resistant metal layer and silicon oxide layer comprise multiple layers to provide pinhole coverage and in which at least one of the corrosion resistant metal layers extends over said inner edges of at least one of the metal protective layers and silicon oxide layers.

Claim 26

A semiconductor device as in claim 6 in which said metal layer has outer edges spaced from said bond pad area and in which said metal layer extends over said inner edges of said oxide layer and said protective layer is a dielectric insulating layer which extends over said outer edges of said metal layer to provide, in combination, said sealing means.

Claim 27

A semiconductor device as in claim 6 in which said metal layer has outer edges spaced from said bond pad area and in which said metal layer extends over said inner edges of said oxide layer and said protective layer is a silicon oxide layer which extends over said outer edges of said metal layer to provide, in combination, said sealing means.

Claim 28

A semiconductor device as in claim 6 in which said protective layer is a metal protective layer and said sealing means comprises an insulating layer which extends over said inner edges of said oxide layer and said inner edges of the metal protective layer.

Claim 29

A semiconductor device as in claim 12 in which said first metal layer extends over said inner edges of said oxide layer and said protective layer is an insulating layer.

Claim 30

A semiconductor device as in claim 12 in which said first metal layer extends over said inner edges of said oxide layer and said protective layer is a silicon oxide layer.

Claim 31

A semiconductor device as in claim 12 in which said protective layer is a metal protective layer.