US5901304A
Expired / Lapsed
US
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Emulating quasi-synchronous DRAM with asynchronous DRAM
Assignee: International Business Machines Corp
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Filing: 1997-03-13
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Granted: 1999-05-04
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Expires: 2017-03-13
Abstract
Abstract A quasi-synchronous DRAM circuit uses a plurality of asynchronous DRAM macros organized in memory banks. An interface conversion circuit receives external synchronous control signals and generates internal control signals for each of the plurality of asynchronous DRAM macros. A data buffer circuit is connected to each of the asynchronous DRAM macros by in internal input/output (I/O) bus. The interface conversion circuit controls the data buffer to provide synchronous burst of data through frequency conversion.
Inventors
- 👤 Wei Hwang
- 👤 Rajiv Vasant Joshi
- 👤 Yasunao Katayama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 17:34
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/1668; G06F13/1689; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C7/00; G11C7/10; G11C7/1072; G11C7/22; G11C8/00; G11C8/12; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
73 words
A quasi-synchronous DRAM circuit comprising: a plurality of asynchronous DRAM macros organized in memory banks; an interface conversion circuit receiving external synchronous control signals and generating internal control signals for each of the plurality of asynchronous DRAM macros; and a data buffer circuit connected to each of the asynchronous DRAM macros by in internal input/output (I/O) bus and controlled by the interface conversion circuit to provide synchronous burst of data through frequency conversion.
Claim 2
Dependent Claim
73 words
A quasi-synchronous DRAM circuit comprising: a plurality of asynchronous DRAM macros organized in memory banks; an interface conversion circuit receiving external synchronous control signals and generating internal control signals for each of the plurality of asynchronous DRAM macros; and a data buffer circuit connected to each of the asynchronous DRAM macros by in internal input/output (I/O) bus and controlled by the interface conversion circuit to provide synchronous burst of data through frequency conversion.
Claim 3
Dependent Claim
25 words
The quasi-synchronous DRAM circuit recited in claim 1 wherein the interface conversion circuit controls the memory banks independently of one another using separate control signals.
Claim 4
Dependent Claim
33 words
The quasi-synchronous DRAM circuit recited in claim 1 wherein the interface conversion circuit and the data buffer circuit are optionally disabled to use the quasi-synchronous DRAM circuit as a conventional asynchronous DRAM circuit.
Claim 5
Dependent Claim
44 words
The quasi-synchronous DRAM circuit recited in claim 1 wherein the data buffer circuit comprises high-speed bidirectional circuits, including off-chip drivers for transferring data from the DRAM macros to I/O pads and input buffers for transferring data from the I/O pads to the DRAM macros.
Claim 6
Dependent Claim
44 words
The quasi-synchronous DRAM circuit recited in claim 4 wherein the data buffer circuit further includes high-speed bus and multiplexer circuits for transferring data between the DRAM macros and the off-chip drivers and input buffers, the multiplexer circuits being controlled by the interface conversion circuit.
Claim 7
Dependent Claim
59 words
The quasi-synchronous DRAM circuit recited in claim 5 wherein the interface conversion circuit comprises: a plurality of input buffer circuits for receiving external control and address signals; and a command decoder connected to receive the external control and address signals and generating separate control signals to independently control the memory banks and control signals for the data buffer circuit.
Claim 8
Dependent Claim
35 words
The quasi-synchronous DRAM circuit recited in claim 6 wherein the command decoder comprises: a state machine implemented in a gate-array design; and combination logic receiving outputs of the state machine and generating the control signals.
Claim 9
Dependent Claim
15 words
the quasi-synchronous DRAM circuit recited in claim 7 implemented in a single integrated circuit package.
Claim 10
Dependent Claim
20 words
The quasi-synchronous DRAM circuit recited in claim 8 wherein the integrated circuit package includes processor core logic and peripheral circuitry.
Claim 11
Dependent Claim
46 words
The quasi-synchronous DRAM circuit recited in claim 7 wherein the DRAM macros are implemented as a plurality of DRAM chips mounted on a memory module and the interface conversion circuit and data buffer circuit are implemented as application specific integrated circuits mounted on the memory module.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-05-03 | 2002-11-02 | 2003-05-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-05-03 | 2006-11-02 | 2007-05-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-05-03 | 2010-11-02 | 2011-05-04 | $7700.00 | Window Closed / Lapsed |