US5901111A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Enhanced multiple block writes to adjacent block of memory using a sequential counter
Assignee: Round Rock Research LLC
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Filing: 1997-08-07
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Granted: 1999-05-04
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Expires: 2017-08-07
Abstract
Abstract A memory device includes an array of randomly addressable registers. Blocks of the addressable registers are addressable by an address for block writing during a block write cycle. The blocks are of the size n, wherein n is the number of bits per plane of memory being written during the block write cycle. The device further includes a sequential counter for incrementing the address by n during burst mode when a block write is performed during a block write cycle to address a next addressable register of the array of randomly addressable registers.
Inventors
- 👤 Loren L. McLaury
- 👤 Donald M. Morgan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 13:24
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C7/00; G11C7/10; G11C7/1015; G11C7/1018; G11C7/1021; G11C7/1075; G11C8/00; G11C8/04; G11C8/12
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
78 words
An integrated circuit, comprising: an array of randomly addressable registers arranged in rows and columns, wherein each of the randomly addressable registers is addressable by a row and a column address; a counter, operatively coupled to the array, that increments the column address of the row by n, wherein n generally corresponds to n=2 x and x is a number of addresses ignored to create a block of randomly addressable registers written during a block write mode operation.
Claim 2
Dependent Claim
78 words
An integrated circuit, comprising: an array of randomly addressable registers arranged in rows and columns, wherein each of the randomly addressable registers is addressable by a row and a column address; a counter, operatively coupled to the array, that increments the column address of the row by n, wherein n generally corresponds to n=2 x and x is a number of addresses ignored to create a block of randomly addressable registers written during a block write mode operation.
Claim 3
Dependent Claim
119 words
An integrated circuit, comprising: an array of randomly addressable registers arranged in rows and columns, wherein each of the randomly addressable registers is addressable by a row and a column address; and a counter, operatively coupled to the array, including: a plurality of flip flops, wherein each flip flop is operatively coupled to every other flip flop; mode control logic having a plurality of outputs; wherein the counter can be incremented by n, wherein n generally corresponds to n=2 x , and x is a number of addresses ignored to create a block of randomly addressable registers written during a block write mode operation; and wherein n corresponds to the signals provided from the outputs to the flip flops.
Claim 4
Dependent Claim
119 words
An integrated circuit, comprising: an array of randomly addressable registers arranged in rows and columns, wherein each of the randomly addressable registers is addressable by a row and a column address; and a counter, operatively coupled to the array, including: a plurality of flip flops, wherein each flip flop is operatively coupled to every other flip flop; mode control logic having a plurality of outputs; wherein the counter can be incremented by n, wherein n generally corresponds to n=2 x , and x is a number of addresses ignored to create a block of randomly addressable registers written during a block write mode operation; and wherein n corresponds to the signals provided from the outputs to the flip flops.
Claim 5
Dependent Claim
119 words
The integrated circuit of claim 2, further comprising: a plurality of look ahead units, wherein each look ahead unit is operatively coupled to two flip flops, and another look ahead unit; a plurality of OR gates, wherein each OR gate is operatively coupled to a look ahead unit and an output; a plurality of AND gates, wherein each AND gate is operatively coupled to a unique OR gate and to two flip flops, and is connected to the mode control logic; a first NOR gate operatively coupled to the outputs and an AND gate; a second NOR gate operatively coupled to two outputs and an AND gate; and an inverter operatively coupled to an output and an AND gate.
Claim 6
Dependent Claim
93 words
The integrated circuit of claim 2, further comprising: a plurality of look ahead units, wherein each look ahead unit is operatively coupled to two flip flops, and another look ahead unit; a plurality of OR gates, wherein each OR gate is operatively coupled to a look ahead unit and an output; a plurality of AND gates, wherein each AND gate is operatively coupled to a unique OR gate and to two flip flops, and is connected to the mode control logic; and wherein each output is operatively coupled to a unique flip flop.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-05-03 | 2002-11-02 | 2003-05-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-05-03 | 2006-11-02 | 2007-05-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-05-03 | 2010-11-02 | 2011-05-04 | $7700.00 | Window Closed / Lapsed |