US5901095A
Expired / Lapsed
US
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Reprogrammable address selector for an embedded DRAM
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1997-12-23
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Granted: 1999-05-04
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Expires: 2017-12-23
Abstract
Abstract A reprogrammable address selector is incorporated in an embedded DRAM array which has a plurality of addressable DRAM components. The reprogrammable address selector responds to an address signal defining a unique response address. One of a plurality of selected response addresses may be electrically and selectively programmed into the selector as a substitute for a fixed response address. Thereafter the addressable DRAM component responds to the programmed response address rather than the fixed response address. The programmed response address is programmed from address signals applied on the bus.
Inventors
- 👤 Harold S. Crafts
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 11:29
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/88; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/408; G11C11/4087
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
100 words
A DRAM array having a plurality of addressable DRAM components embedded in an IC, comprising: a bus having a plurality of conductors on which address, control and data signals are applied; and a reprogrammable address selector associated with each addressable DRAM component and connected to the bus and responsive to an address signal defining a unique response address; each reprogrammable address selector including a programmable address circuit in which to program one of a plurality of selected response addresses, and selecting the associated addressable DRAM component in response to address signals on the bus corresponding to the programmed response address.
Claim 2
Dependent Claim
100 words
A DRAM array having a plurality of addressable DRAM components embedded in an IC, comprising: a bus having a plurality of conductors on which address, control and data signals are applied; and a reprogrammable address selector associated with each addressable DRAM component and connected to the bus and responsive to an address signal defining a unique response address; each reprogrammable address selector including a programmable address circuit in which to program one of a plurality of selected response addresses, and selecting the associated addressable DRAM component in response to address signals on the bus corresponding to the programmed response address.
Claim 3
Dependent Claim
26 words
A DRAM array as defined in claim 1 wherein: the programmed response address is programmed into the address circuit by address signals supplied on the bus.
Claim 4
Dependent Claim
40 words
A DRAM array as defined in claim 1 wherein: the reprogrammable address selector has a fixed response address and responds to address signals corresponding to the fixed response address to substitute the programmed response address for the fixed response address.
Claim 5
Dependent Claim
34 words
A DRAM array as defined in claim 3 wherein: the reprogrammable address selector is selectively disabled from responding to the fixed response address after the programmed response address is programmed into the address circuit.
Claim 6
Dependent Claim
34 words
A DRAM array as defined in claim 3 wherein the programmed response address is programmed into the address circuit after the address signal corresponding to the fixed response address is supplied on the bus.
Claim 7
Dependent Claim
58 words
A DRAM array as defined in claim 5 wherein the address, control and data signals are applied on the bus at bus cycle intervals, and wherein: the address signals defining the programmed response address are applied on the bus in the next following bus cycle after the signals defining the fixed response address are applied on the bus.
Claim 8
Dependent Claim
20 words
A DRAM array as defined in claim 3 wherein: the addressable DRAM component is a DRAM segment of the array.
Claim 9
Dependent Claim
60 words
A DRAM array as defined in claim 7 wherein the address signals include segment address signals, word line address signals and bit line address signals, and the IC includes a processor which executes operational software and uses DRAM segment addresses in a range of a continuous memory map, and wherein: the programmed response address falls within the continuous memory map.
Claim 10
Dependent Claim
67 words
A DRAM array as defined in claim 8 wherein the DRAM array includes redundant DRAM segments, and wherein: the programmed response address of one redundant DRAM segment is within the range of the continuous memory map; and one DRAM segment having a fixed response address within the range of the continuous memory map has a programmed response address outside of the range of the continuous memory map.
Claim 11
Dependent Claim
30 words
A DRAM array as defined in claim 7 wherein: the address circuit includes a register within which to record the programmed response address; and the register is a non-volatile memory.
Claim 12
Dependent Claim
62 words
A DRAM array as defined in claim 3 wherein the reprogrammable address selector: supplies a control signal in response to the receipt of address signals corresponding to the fixed response address; and substitutes the programmed response address for the fixed response address in response to the control signal and the receipt of address signals corresponding to the programmed address on the bus.
Claim 13
Dependent Claim
21 words
A DRAM array as defined in claim 3 wherein: the addressable DRAM component comprises a word line decoder of the array.
Claim 14
Dependent Claim
21 words
A DRAM array as defined in claim 3 wherein: the addressable DRAM component comprises a bit line decoder of the array.
Claim 15
Dependent Claim
27 words
A DRAM array as defined in claim 3 wherein: the programmed response address programmed into the address circuit is the same address as the fixed response address.
Claim 16
Dependent Claim
46 words
A DRAM array as defined in claim 1, wherein: the addressable DRAM components are DRAM memory segments; and further comprising: a power control circuit operative in response to control signals applied on the bus to electrically disconnect power from a selected one of the DRAM segments.
Claim 17
Independent Claim
86 words
A method of reprogramming a response address of an addressable DRAM component of a DRAM array embedded in an IC which has a bus, comprising the steps of: applying address, control and data signals on the bus; associating a unique response address with each addressable DRAM component in the IC; programming the addressable DRAM component to respond to one of a plurality of selected response addresses; and selecting the addressable DRAM component in response to address signals on the bus corresponding to the programmed response address.
Claim 18
Independent Claim
86 words
A method of reprogramming a response address of an addressable DRAM component of a DRAM array embedded in an IC which has a bus, comprising the steps of: applying address, control and data signals on the bus; associating a unique response address with each addressable DRAM component in the IC; programming the addressable DRAM component to respond to one of a plurality of selected response addresses; and selecting the addressable DRAM component in response to address signals on the bus corresponding to the programmed response address.
Claim 19
Dependent Claim
30 words
A method as defined in claim 16 further comprising the step of: programming the programmed response address by applying address signals on the bus corresponding to the programmed response address.
Claim 20
Dependent Claim
39 words
A method as defined in claim 16 further comprising the steps of: establishing a fixed response address for each addressable DRAM component; and substituting the programmed response address for the fixed response address during operation of the DRAM array.
Claim 21
Dependent Claim
33 words
A method as defined in claim 18 further comprising the step of: disabling the addressable DRAM component from responding to the fixed response address signals after the programmed response address as been programmed.
Claim 22
Dependent Claim
32 words
A method as defined in claim 18 further comprising the steps of: programming the programmed response address after the address signal corresponding to the fixed response address is supplied on the bus.
Claim 23
Dependent Claim
75 words
A method as defined in claim 18 wherein the addressable DRAM component is a DRAM segment of the array, the address signals include segment address signals, word line address signals and bit line address signals, the IC includes a processor which executes operational software and uses DRAM segment addresses in a range of a continuous memory map, and said method further comprises the step of: programming the programmed response address within the continuous memory map.
Claim 24
Dependent Claim
80 words
A method as defined in claim 21 wherein the DRAM array comprises a plurality of redundant DRAM segments, and said method further comprising the step of: programming the response address of one redundant DRAM segment within the range of the continuous memory map; and programming the response address of one other DRAM segment having a fixed response address within the range of the continuous memory map to a programmed response address outside of the range of the continuous memory map.
Claim 25
Dependent Claim
26 words
A method as defined in claim 18 further comprising the step of: programming the programmed response address to the same address as the fixed response address.
Claim 26
Dependent Claim
67 words
A method as defined in claim 18 wherein the addressable DRAM component is a DRAM segment of the array, the DRAM array includes a plurality of DRAM segments, the address signals include segment address signals, and said method further comprises the steps of: programming the same programmed response address for the segment address signals into each DRAM segment; and conducting a functional test of the DRAM array.
Claim 27
Dependent Claim
104 words
A method as defined in claim 18 wherein the addressable DRAM component is a DRAM segment of the array, the DRAM array includes a plurality of DRAM segments, the address signals include segment address signals, the IC includes a processor which executes operational software, and said method further comprises the steps of: programming the same programmed response addresses for the segment address signals into at least two DRAM segments; and combining data read from the at least two DRAM segments into a word of bit length greater than the bit length of the data read from any of the at least two DRAM segments.
Claim 28
Dependent Claim
136 words
A method as defined in claim 18 wherein the addressable DRAM component is a DRAM segment of the array, the DRAM array includes a plurality of DRAM segments, the address signals include segment address signals, the IC includes a processor which executes operational software, and said method further comprises the steps of: programming the same programmed response addresses for the segment address signals into at least two DRAM segments; combining data read from the at least two DRAM segments into a word of bit length greater than the bit length of the data read from any of the at least two DRAM segments during execution of a portion of the operational software; and using a word of the length of the data read from another DRAM segment during execution of another portion of the operational software.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-05-03 | 2002-11-02 | 2003-05-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-05-03 | 2006-11-02 | 2007-05-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-05-03 | 2010-11-02 | 2011-05-04 | $7700.00 | Window Closed / Lapsed |