US5898710A
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Implied interleaving, a family of systematic interleavers and deinterleavers
Assignee: Ikanos Communications Inc
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Filing: 1995-06-06
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Granted: 1999-04-27
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Expires: 2015-06-06
Abstract
Abstract Apparatus that realizes a substantial advantage by employing implied interleaving to create a systematic interleaver, that can result in a superior block error rate compared to the current data interleaving techniques in which uncorrected error bursts are distributed by the deinterleaver. The disclosed principles lead to a embodiments that essentially eliminate transmitter memory regardless of the interleaving approach employed. By way of example, block interleaving (regular or random), convolutional interleaving (regular and random) and product interleaving approaches are described. In implied interleaving, all incoming data is treated as if it is pre-interleaved and transmitted directly to its destination without alteration to its sequence, and essentially without delay. Concurrently with the transmission of the data, the data is applied to apparatus that treats the data as if it had been interleaved in accordance with a selected interleaving approach and, in accordance with such treatment, redundant symbols are generated and inserted into the transmitted data stream. At the receiver, the incoming data is delayed, corrected, and the information symbols in the incoming data are delivered to the user, corrected as necessary, in the same order as the information symbols arrived at the receiver.
Inventors
- 👤 Daniel Amrany
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 00:02
CPC Classifications
H; H03; H03M; H03M13/00; H03M13/27; H03M13/2742; H03M13/2703; H03M13/2732
Claims Analysis
Total Claims: 37
Claim 1
Independent Claim
131 words
An encoder comprising: a memory; and processing means coupled to the memory including a) means for writing incoming symbols into the memory, b) means for outputting symbols out of the memory at rate higher than the rate of writing into the memory, and applying the read symbols to a channel, c) means for implementing D encoders (D being an integer) in the processing means cooperating with the memory, by employing the read symbols in calculations aimed at developing redundant symbols, where each set of D×K consecutive symbols are distributed to different ones of the implemented D encoders such that at least one pair of consecutive symbols are applied to a particular one of said D encoders, where K is the number of symbols in a codeword, exclusive of the redundant symbols.
Claim 2
Dependent Claim
131 words
An encoder comprising: a memory; and processing means coupled to the memory including a) means for writing incoming symbols into the memory, b) means for outputting symbols out of the memory at rate higher than the rate of writing into the memory, and applying the read symbols to a channel, c) means for implementing D encoders (D being an integer) in the processing means cooperating with the memory, by employing the read symbols in calculations aimed at developing redundant symbols, where each set of D×K consecutive symbols are distributed to different ones of the implemented D encoders such that at least one pair of consecutive symbols are applied to a particular one of said D encoders, where K is the number of symbols in a codeword, exclusive of the redundant symbols.
Claim 3
Dependent Claim
126 words
An encoder comprising: a memory; and processing means coupled to the memory including a) means for writing incoming symbols into the memory, b) means for outputting symbols out of the memory at rate higher than the rate of writing into the memory, and applying the read symbols to a channel, c) means for implementing D encoders (D being an integer) in the processing means cooperating with the memory, by employing the read symbols in calculations aimed at developing redundant symbols, where each set of D consecutive symbols are distributed to different ones of the implemented D encoders, and d) means for applying the redundant symbols to the channel, where the calculations for the D encoders are reset in accordance with a selected implied convolutional interleaving schema.
Claim 4
Dependent Claim
126 words
An encoder comprising: a memory; and processing means coupled to the memory including a) means for writing incoming symbols into the memory, b) means for outputting symbols out of the memory at rate higher than the rate of writing into the memory, and applying the read symbols to a channel, c) means for implementing D encoders (D being an integer) in the processing means cooperating with the memory, by employing the read symbols in calculations aimed at developing redundant symbols, where each set of D consecutive symbols are distributed to different ones of the implemented D encoders, and d) means for applying the redundant symbols to the channel, where the calculations for the D encoders are reset in accordance with a selected implied convolutional interleaving schema.
Claim 5
Dependent Claim
45 words
An encoder according to claim 2 where, under control of the processing means, in addition to each set of D consecutive symbols being distributed to different ones of the implemented D encoders, each (D+1) th symbol is employed in the calculations of a particular encoder.
Claim 6
Dependent Claim
52 words
An encoder according to claim 2 where, under control of the processing means, in addition to each set of D consecutive symbols being distributed to different ones of the implemented D encoders, at least one set that contains each (D+1) th symbol is employed in the calculations of more than one encoder.
Claim 7
Dependent Claim
49 words
An encoder according to claim 2 where incoming symbols are written into a data buffering region of the memory, symbols are read out of the data buffering region, and implementation of the D encoders involves storage of calculation results, which results are stored in another region of the memory.
Claim 8
Dependent Claim
26 words
The encoder of claim 2 where the reading out of symbols out of the memory is in the same order as symbols written into the memory.
Claim 9
Dependent Claim
14 words
The encoder of claim 2 further comprising means for block encoding said incoming signals.
Claim 10
Dependent Claim
18 words
The encoder of claim 7 wherein said block interleaving and said convolutional interleaving form a product encoding arrangement.
Claim 11
Dependent Claim
135 words
An encoder comprising: a memory; and processing means coupled to the memory for a) writing incoming symbols into the memory, b) outputting symbols out of the memory at a rate higher than the rate of writing into the memory, and applying the read symbols to a channel, c) implementing D encoders (D being an integer) by employing the read symbols in calculations aimed at developing redundant symbols, where each set of D consecutive symbols are distributed to different ones of the implemented D encoders and each Dth symbol is employed in the calculations of a particular encoder, and d) applying redundant symbols to the channel, where the calculations for the D encoders are reset in accordance with a selected implied interleaving approach from a set that includes regular convolutional implied interleaving and block implied interleaving.
Claim 12
Dependent Claim
135 words
An encoder comprising: a memory; and processing means coupled to the memory for a) writing incoming symbols into the memory, b) outputting symbols out of the memory at a rate higher than the rate of writing into the memory, and applying the read symbols to a channel, c) implementing D encoders (D being an integer) by employing the read symbols in calculations aimed at developing redundant symbols, where each set of D consecutive symbols are distributed to different ones of the implemented D encoders and each Dth symbol is employed in the calculations of a particular encoder, and d) applying redundant symbols to the channel, where the calculations for the D encoders are reset in accordance with a selected implied interleaving approach from a set that includes regular convolutional implied interleaving and block implied interleaving.
Claim 13
Dependent Claim
17 words
An encoder according to claim 9 where the set of implied interleaving approaches includes random convolutional interleaving.
Claim 14
Dependent Claim
191 words
An implied interleaving encoder responsive to a stream of incoming data symbols that is assumed to comprise codewords having N symbols which include redundant symbols and which are interleaved in a convolutional interleaving pattern to an interleaving depth D, for developing the redundant symbols for each of the codewords and inserting them in the stream of incoming data symbols in accordance with the interleaving pattern, including a first memory for buffering symbols of the incoming data; a plurality of D encoders, each of which develops a set of at least one redundant symbol corresponding to a sequence of symbols that define a data portion of a codeword; a first router responsive to output data of the first memory for delivering successive symbols to different ones of the D encoders in a cyclic manner; and a combiner, responsive to the redundant symbols developed by the D encoders and to output data of the first memory, for applying information arriving at the combiner to a channel, where each of the D encoders is arranged to handle codewords that are offset from the codewords handled by the other encoders by at least two symbols.
Claim 15
Dependent Claim
191 words
An implied interleaving encoder responsive to a stream of incoming data symbols that is assumed to comprise codewords having N symbols which include redundant symbols and which are interleaved in a convolutional interleaving pattern to an interleaving depth D, for developing the redundant symbols for each of the codewords and inserting them in the stream of incoming data symbols in accordance with the interleaving pattern, including a first memory for buffering symbols of the incoming data; a plurality of D encoders, each of which develops a set of at least one redundant symbol corresponding to a sequence of symbols that define a data portion of a codeword; a first router responsive to output data of the first memory for delivering successive symbols to different ones of the D encoders in a cyclic manner; and a combiner, responsive to the redundant symbols developed by the D encoders and to output data of the first memory, for applying information arriving at the combiner to a channel, where each of the D encoders is arranged to handle codewords that are offset from the codewords handled by the other encoders by at least two symbols.
Claim 16
Dependent Claim
204 words
An implied interleaving encoder responsive to a stream of incoming data symbols that is assumed to comprise codewords having N symbols which include redundant symbols and which are interleaved in a product interleaving pattern to an interleaving depth D, for developing the redundant symbols for each of the codewords and inserting them in the stream of incoming data symbols in accordance with the interleaving pattern, including a first memory for buffering symbols of the incoming data; a plurality of D encoders, each of which develops a set of at least one redundant symbol corresponding to a sequence of symbols that define a data portion of a codeword; an additional encoder responsive to all output data of the first memory for developing at least one additional redundant symbol for each set of preselected number of symbols delivered by the first memory; a first router, responsive to output data of the first memory for delivering successive symbols to different ones of the D encoders in cyclic manner; a combiner, responsive to the redundant symbols developed by the D encoders, to the redundant symbols developed by the additional encoder, and to output data of the first memory, for applying information arriving at the combiner to a channel.
Claim 17
Dependent Claim
204 words
An implied interleaving encoder responsive to a stream of incoming data symbols that is assumed to comprise codewords having N symbols which include redundant symbols and which are interleaved in a product interleaving pattern to an interleaving depth D, for developing the redundant symbols for each of the codewords and inserting them in the stream of incoming data symbols in accordance with the interleaving pattern, including a first memory for buffering symbols of the incoming data; a plurality of D encoders, each of which develops a set of at least one redundant symbol corresponding to a sequence of symbols that define a data portion of a codeword; an additional encoder responsive to all output data of the first memory for developing at least one additional redundant symbol for each set of preselected number of symbols delivered by the first memory; a first router, responsive to output data of the first memory for delivering successive symbols to different ones of the D encoders in cyclic manner; a combiner, responsive to the redundant symbols developed by the D encoders, to the redundant symbols developed by the additional encoder, and to output data of the first memory, for applying information arriving at the combiner to a channel.
Claim 18
Dependent Claim
36 words
The encoder of claim 12 where each of the D encoders are arranged to handle codewords that are offset from the codewords handled by the remaining ones of said D encoders by at least two symbols.
Claim 19
Dependent Claim
128 words
A systematic convolutional system comprising: a plurality of encoders, where each of the encoders outputs the signals applied to the encoder, in the order the signals are applied to the encoder, as well as redundant signals that are developed from a preselected number of the input signals applied to the encoder following a reset signal applied to the encoder; means for dispersing applied input signals to said plurality of encoders, where the applied input signals arrive at a predetermined rate; means for combining the output signals of the plurality of encoders; and means for applying a reset signal to at least one of the encoders that is staggered from the other reset signals by more than one period of the rate of arrival of the applied input signals.
Claim 20
Dependent Claim
128 words
A systematic convolutional system comprising: a plurality of encoders, where each of the encoders outputs the signals applied to the encoder, in the order the signals are applied to the encoder, as well as redundant signals that are developed from a preselected number of the input signals applied to the encoder following a reset signal applied to the encoder; means for dispersing applied input signals to said plurality of encoders, where the applied input signals arrive at a predetermined rate; means for combining the output signals of the plurality of encoders; and means for applying a reset signal to at least one of the encoders that is staggered from the other reset signals by more than one period of the rate of arrival of the applied input signals.
Claim 21
Independent Claim
122 words
A method for encoding and interleaving an applied sequence of input signals arriving at regular intervals, the sequence having a given order, to develop an interleaved output signal comprising the input signals in a sequence having the same given order, the method comprising the steps of: routing the input signals to a plurality of encoders; in response to the input signals routed to the encoders, the encoders developing a selected number of redundant signals and outputting the redundant signals, where the inserting of redundant signals by any one of the encoders is staggered in time relative to any other one of the encoders by more than one of said intervals; and routing the output signals of the encoders to an output port.
Claim 22
Independent Claim
122 words
A method for encoding and interleaving an applied sequence of input signals arriving at regular intervals, the sequence having a given order, to develop an interleaved output signal comprising the input signals in a sequence having the same given order, the method comprising the steps of: routing the input signals to a plurality of encoders; in response to the input signals routed to the encoders, the encoders developing a selected number of redundant signals and outputting the redundant signals, where the inserting of redundant signals by any one of the encoders is staggered in time relative to any other one of the encoders by more than one of said intervals; and routing the output signals of the encoders to an output port.
Claim 23
Dependent Claim
126 words
An encoder comprising: a memory; and processing means coupled to the memory including a) means for writing incoming symbols into the memory, b) means for outputting symbols out of the memory at rate higher than the rate of writing into the memory, and applying the read symbols to a channel, c) means for implementing D encoders (D being an integer) in the processing means cooperating with the memory, by employing the read symbols in calculations aimed at developing redundant symbols, where each set of D consecutive symbols are distributed to different ones of the implemented D encoders, and d) means for applying the redundant symbols to the channel, where the calculations for the D encoders are reset in accordance with a selected implied random interleaving schema.
Claim 24
Dependent Claim
126 words
An encoder comprising: a memory; and processing means coupled to the memory including a) means for writing incoming symbols into the memory, b) means for outputting symbols out of the memory at rate higher than the rate of writing into the memory, and applying the read symbols to a channel, c) means for implementing D encoders (D being an integer) in the processing means cooperating with the memory, by employing the read symbols in calculations aimed at developing redundant symbols, where each set of D consecutive symbols are distributed to different ones of the implemented D encoders, and d) means for applying the redundant symbols to the channel, where the calculations for the D encoders are reset in accordance with a selected implied random interleaving schema.
Claim 25
Dependent Claim
152 words
An implied interleaving encoder for creating a data stream output having segments of data and segments of error correction information, comprising: a buffer memory adapted to receive and delay a data input communicated at a first bit rate, the buffer memory outputting the data in segments at a second bit rate which is faster than the first bit rate; an implied interleaving circuit electrically coupled to the buffer memory, the implied interleaving circuit being adapted to generate the segments of error correction information based on the segments of the data; and a multiplexing circuit electrically coupled to the buffer memory and the implied interleaving circuit, the multiplexing circuit being adapted to create the data stream by alternatively trasmitting the segments of data from the buffer memory and the segments of error correction information from the implied interleaving circuit into a single data communications channel, wherein the sequence of the data is unchanged.
Claim 26
Dependent Claim
152 words
An implied interleaving encoder for creating a data stream output having segments of data and segments of error correction information, comprising: a buffer memory adapted to receive and delay a data input communicated at a first bit rate, the buffer memory outputting the data in segments at a second bit rate which is faster than the first bit rate; an implied interleaving circuit electrically coupled to the buffer memory, the implied interleaving circuit being adapted to generate the segments of error correction information based on the segments of the data; and a multiplexing circuit electrically coupled to the buffer memory and the implied interleaving circuit, the multiplexing circuit being adapted to create the data stream by alternatively trasmitting the segments of data from the buffer memory and the segments of error correction information from the implied interleaving circuit into a single data communications channel, wherein the sequence of the data is unchanged.
Claim 27
Dependent Claim
76 words
The implied interleaving encoder of claim 17, wherein the implied interleaving circuit further comprises: at least one encoder adapted to generate error correction data from a data input; a router adapted to distribute the data in the data segments to the at least one encoder according to a predetermined interleaving scheme; and a combiner adapted to generate the segments of error correction information by collecting the error correction data generated by the at least one encoder.
Claim 28
Dependent Claim
15 words
The implied interleaving encoder of claim 18, wherein the predetermined interleaving scheme is convolutional interleaving.
Claim 29
Dependent Claim
15 words
The implied interleaving encoder of claim 19, wherein the predetermined interleaving scheme is block interleaving.
Claim 30
Dependent Claim
112 words
An implied interleaving encoder for creating a data stream output having segments of data and segments of error correction information, comprising: a means for receiving and delaying a data input communicated at a first bit rate; a means for transmitting the data in segments at a second bit rate, the second bit rate being greater than the first bit rate; a means for generating segments of error correction information based on the segments of the data using a predetermined implied interleaving scheme; and a means for alternatively transmitting the segments of data and the segments of error correction information into a data communications channel, wherein the sequence of the data is unchanged.
Claim 31
Dependent Claim
112 words
An implied interleaving encoder for creating a data stream output having segments of data and segments of error correction information, comprising: a means for receiving and delaying a data input communicated at a first bit rate; a means for transmitting the data in segments at a second bit rate, the second bit rate being greater than the first bit rate; a means for generating segments of error correction information based on the segments of the data using a predetermined implied interleaving scheme; and a means for alternatively transmitting the segments of data and the segments of error correction information into a data communications channel, wherein the sequence of the data is unchanged.
Claim 32
Dependent Claim
79 words
The implied interleaving encoder of claim 21, wherein the means for generating segments of error correction information further comprises: a plurality of encoders adapted to generate error correction data from a data input; a router adapted to distribute the data in the data segments among the plurality of encoders according to a predetermined interleaving scheme; and a combiner adapted to generate the segments of error correction information by collecting the error correction data generated by the plurality of encoders.
Claim 33
Dependent Claim
15 words
The implied interleaving encoder of claim 22, wherein the predetermined interleaving scheme is block interleaving.
Claim 34
Dependent Claim
15 words
The implied interleaving encoder of claim 22, wherein the predetermined interleaving scheme is convolutional interleaving.
Claim 35
Independent Claim
104 words
An method for creating a data stream output having segments of data and segments of error correction information using implied interleaving, comprising the steps of: receiving and delaying a data input communicated at a first bit rate; transmitting the data in segments at a second bit rate, the second bit rate being greater than the first bit rate; generating segments of error correction information based on the segments of the data using a predetermined implied interleaving scheme; and alternatively transmitting the segments of data and the segments of error correction information into a data communications channel, wherein the sequence of the data is unchanged.
Claim 36
Independent Claim
104 words
An method for creating a data stream output having segments of data and segments of error correction information using implied interleaving, comprising the steps of: receiving and delaying a data input communicated at a first bit rate; transmitting the data in segments at a second bit rate, the second bit rate being greater than the first bit rate; generating segments of error correction information based on the segments of the data using a predetermined implied interleaving scheme; and alternatively transmitting the segments of data and the segments of error correction information into a data communications channel, wherein the sequence of the data is unchanged.
Claim 37
Dependent Claim
65 words
The method claim 25, wherein the step of generating segments of error correction information further comprises the steps of: distributing the data in the data segments among a plurality of encoders according to a predetermined interleaving scheme; generating error correction data from the distributed data; and generating the segments of error correction information by collecting the error correction data generated by the plurality of encoders.
References Cited (Backward Citations)
EP0086566A2
Cited
JPS6059468A
Cited
EP0202571A2
Cited
US5063533A
Cited
US5224106A
Cited
US5204876A
Cited
US5572532A
Cited
US5537420A
Cited
US5592492A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-04-26 | 2002-10-26 | 2003-04-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-04-26 | 2006-10-26 | 2007-04-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-04-26 | 2010-10-26 | 2011-04-27 | $7700.00 | Window Closed / Lapsed |