US5063533A — Reconfigurable deinterleaver/interleaver for bloc…

Claim 1

Independent Claim 207 words

A random access memory comprising: a plurality of memory cells configured as an array of N bit rows by M bit columns (where M and N are positive integers), each memory cell having an input for writing a data bit, and an output for reading the data bit; a plurality of write enable devices, each having a write enable input, a write data input, and a write data output, said write data output of each device being coupled to an individual one of said memory cell inputs; M data input lines, each of said data input lines being coupled to a row of write data inputs; N write enable input lines, each of said write enable input lines being coupled to a column of write enable inputs; a plurality of read enable devices, each having a read enable input, a read data input, and a read data output, said read data input of each device being coupled to an individual one of said memory cell outputs; N data output lines, each of said data output lines being coupled to a column of read data outputs; and M read enable input lines, each of said read enable input lines being coupled to a row of read enable inputs.

Claim 2

Dependent Claim 207 words

A random access memory comprising: a plurality of memory cells configured as an array of N bit rows by M bit columns (where M and N are positive integers), each memory cell having an input for writing a data bit, and an output for reading the data bit; a plurality of write enable devices, each having a write enable input, a write data input, and a write data output, said write data output of each device being coupled to an individual one of said memory cell inputs; M data input lines, each of said data input lines being coupled to a row of write data inputs; N write enable input lines, each of said write enable input lines being coupled to a column of write enable inputs; a plurality of read enable devices, each having a read enable input, a read data input, and a read data output, said read data input of each device being coupled to an individual one of said memory cell outputs; N data output lines, each of said data output lines being coupled to a column of read data outputs; and M read enable input lines, each of said read enable input lines being coupled to a row of read enable inputs.

Claim 3

Dependent Claim 18 words

The random access memory according to claim 1 wherein the integer N is greater than the integer M.

Claim 4

Dependent Claim 18 words

The random access memory according to claim 1 wherein the integer M is greater than the integer N.

Claim 5

Dependent Claim 18 words

The random access memory according to claim 1 wherein the integer N is equal to the integer M.

Claim 6

Dependent Claim 21 words

The random access memory according to claim 1 wherein each of said write enable devices is an N channel MOS transistor.

Claim 7

Dependent Claim 21 words

The random access memory according to claim 1 wherein each of said read enable devices is an N channel MOS transistor.

Claim 8

Dependent Claim 68 words

The random access memory according to claim 1 wherein after up to N M-bit data words which have been interleaved to degree N are written into said N columns of said memory array, up to M N-bit data words can be read from said M rows of said memory array, the data words being read being deinterleaved to degree M relative the the data words which were written.

Claim 9

Dependent Claim 61 words

The random access memory according to claim 1 wherein after up to M N-bit data words are written into said M rows of said memory array, up to N M-bit data words can be read from said N columns of said memory array, the data words being read being interleaved to degree N relative to the data words which were written.

Claim 10

Dependent Claim 81 words

The random access memory according to claim 1 further comprising M data output lines, each of said data output lines being coupled to a row of write data inputs, whereby up to an M bit codeword is written into one of said N columns of said memory cells for each write enable input line selected, and whereby up to an M bit codeword is read from one of said N columns of said memory cells for each write enable line selected.

Claim 11

Dependent Claim 155 words

A reconfigurable deinterleaver for deinterleaving interleaved data words, comprising: a memory array, having N columns by M rows, the columns being configured to enable writing up to N M-bit interleaved data words therein, the rows being configured to enable reading up to M N-bit data words therefrom, the N-bit data words being deinterleaved relative to the M-bit interleaved data words when the data words are read; programmable memory means for storing predetermined deinterleaver parameters defining the number and length of interleaved data words to be written, and number and length of deinterleaved data words to be read; and controller means, coupled to said memory array, and responsive to the predetermined deinterleaver parameters, for generating write enable signals for controlling the writing of up to N M-bit interleaved data words into said memory array, and for generating read enable signals for controlling the reading of up to M N-bit deinterleaved data words from said memory array.

Claim 12

Dependent Claim 155 words

A reconfigurable deinterleaver for deinterleaving interleaved data words, comprising: a memory array, having N columns by M rows, the columns being configured to enable writing up to N M-bit interleaved data words therein, the rows being configured to enable reading up to M N-bit data words therefrom, the N-bit data words being deinterleaved relative to the M-bit interleaved data words when the data words are read; programmable memory means for storing predetermined deinterleaver parameters defining the number and length of interleaved data words to be written, and number and length of deinterleaved data words to be read; and controller means, coupled to said memory array, and responsive to the predetermined deinterleaver parameters, for generating write enable signals for controlling the writing of up to N M-bit interleaved data words into said memory array, and for generating read enable signals for controlling the reading of up to M N-bit deinterleaved data words from said memory array.

Claim 13

Dependent Claim 25 words

The reconfigurable deinterleaver according to claim 10, wherein said interleaved data words are written in parallel and said deinterleaved data words are read in parallel.

Claim 14

Dependent Claim 63 words

The reconfigurable deinterleaver according to claim 10, wherein said controller means generates data output signals for controlling the reading of interleaved data words from said memory array, and said deinterleaver further comprises row selector means, responsive to the data output signals, for enabling the reading of the deinterleaved data words by selecting L bit segments from each N bit row in a sequence.

Claim 15

Dependent Claim 44 words

The reconfigurable deinterleaver according to claim 12, wherein said row selector means comprises data multiplexer means, coupled to said memory array, for enabling the reading of up to N bit deinterleaved data words by selecting one or more L bit segments in a sequence.

Claim 16

Dependent Claim 18 words

The reconfigurable deinterleaver according to claim 13, wherein each L bit segment is an eight bit data byte.

Claim 17

Dependent Claim 64 words

The reconfigurable deinterleaver according to claim 10, wherein said controller means further generates data input signals for controlling the writing of interleaved data words into said memory array, and said deinterleaver further comprises column selector means, responsive to the data input signals, for enabling the writing of the interleaved data words by selecting L bit segments into each M bit column in a sequence.

Claim 18

Dependent Claim 44 words

The reconfigurable deinterleaver according to claim 15, wherein said column selector means comprises data demultiplexer means, coupled to said memory array, for enabling the writing of up to M bit interleaved data words by selecting one or more L bit segments in a sequence.

Claim 19

Dependent Claim 18 words

The reconfigurable deinterleaver according to claim 16, wherein each L bit segment is an eight bit data byte.

Claim 20

Dependent Claim 97 words

The reconfigurable deinterleaver according to claim 10, wherein said controller means comprises: microcomputer means, responsive to the predetermined deinterleaver parameters for generating a first address range corresponding to the number of columns of said memory array into which interleaved data words is to be written, and a second address range corresponding to the number of rows of said memory array from which deinterleaved data words is to be read; and address decoder means, responsive to the first address range for generating write enable signals and further responsive to the second address range for generating read enable signals.

Claim 21

Dependent Claim 139 words

The reconfigurable deinterleaver according to claim 10, wherein said controller means comprises: microcomputer means, responsive to the predetermined deinterleaver parameters for generating at least one predetermined address for effecting the writing of interleaved data words into said memory array, and for effecting the reading of deinterleaved data words from said memory array; address decoder means, responsive to the at least one predetermined address for generating a deinterleaver enable signal to initiate writing of interleaved data words into said memory array, and further to initiate reading of deinterleaved data words from said memory array; auto incrementing means, responsive to the deinterleaver enable signal, for generating the write enable signals for controlling the writing of interleaved data words into said memory array, and for generating the read enable signals for controlling the reading of deinterleaved data words from said memory array.

Claim 22

Dependent Claim 192 words

The reconfigurable deinterleaver according to claim 19, wherein said auto incrementer means comprises: programmable column counter means, for generating column count signals; column decoder means, responsive to the column count signals, for generating the write enable signals for controlling the writing of interleaved codewords into said memory array; column end count register means, for storing the number of columns of interleaved codewords to be written, up to N, and for generating a column end count signal in response thereto; column count comparator means, response to the column count and column end count signals for generating a write complete signal in response thereto; programmable row counter means, for generating row count signals; row decoder means, responsive to the row count signals, for generating the read enable signals for controlling the reading of interleaved data words from said memory array; row end count register means, for storing the number of deinterleaved data words to be read, up to M, and for generating a row end count signal in response thereto; and row count comparator means, responsive to the row count and row end count signals for generating a read complete signal in response thereto.

Claim 23

Dependent Claim 19 words

The reconfigurable deinterleaver according to claim 20, wherein said programmable column and row counter means are resettable to zero.

Claim 24

Dependent Claim 39 words

The reconfigurable deinterleaver according to claim 21, wherein said programmable column counter means is presettable to a non-zero value less than N and said programmable column and row counter means is presettable to a nonzero value less than M.

Claim 25

Dependent Claim 57 words

The reconfigurable deinterleaver according to claim 10 wherein said deinterleaver further comprises column read data drivers, and wherein said row selector means is further coupled to said column read data drivers and responsive to the data input signals, for enabling the reading of the interleaved codewords by selecting at least a portion of each M bit column.

Claim 26

Dependent Claim 161 words

A reconfigurable interleaver for interleaving data words, comprising: a memory array, having N columns by M rows, the columns being configured to enable writing up to N M-bit data words therein, the rows being configured to enable reading up to M N-bit data words therefrom, the M N-bit data words being interleaved relative to the data words written when the data words are read; programmable memory means for storing predetermined interleaver parameters defining the number and length of non-interleaved codewords (up to N by M) to be written, and number and length of interleaved data words (up to M by N) to be read; and controller means, coupled to said memory array, and responsive to the predetermined interleaver parameters, for generating write enable signals for controlling the writing of up to N M-bit data words into said memory array, and for generating read enable signals for controlling the reading of up to M N-bit interleaved data words from said memory array.

Claim 27

Dependent Claim 161 words

A reconfigurable interleaver for interleaving data words, comprising: a memory array, having N columns by M rows, the columns being configured to enable writing up to N M-bit data words therein, the rows being configured to enable reading up to M N-bit data words therefrom, the M N-bit data words being interleaved relative to the data words written when the data words are read; programmable memory means for storing predetermined interleaver parameters defining the number and length of non-interleaved codewords (up to N by M) to be written, and number and length of interleaved data words (up to M by N) to be read; and controller means, coupled to said memory array, and responsive to the predetermined interleaver parameters, for generating write enable signals for controlling the writing of up to N M-bit data words into said memory array, and for generating read enable signals for controlling the reading of up to M N-bit interleaved data words from said memory array.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1994-11-04	1995-05-06	1995-11-05	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1998-11-04	1999-05-06	1999-11-05	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2002-11-04	2003-05-06	2003-11-05	$7700.00	Window Closed / Lapsed

Reconfigurable deinterleaver/interleaver for block oriented data

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