EP0202571A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Interleaving circuit
Assignee: Panasonic Holdings Corp
•
Filing: 1986-05-12
•
Granted: —
•
Expires: 2006-05-12
Abstract
Abstract In the interleaving circuit, writing and reading are executed on the two dimensions array memory according to a first address sequence and a second address sequence, and product codes errors occurred on the same column are propagated to the columns which are different with each other thereby to scatter the errors to minimize the decrease of the error correction capability of the product codes.
Inventors
- 👤 Yuji Takagi
- 👤 Isao Satoh
- 👤 Tatsuo Sugimura
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 08:43
CPC Classifications
H; H03; H03M; H03M7/00; H03M13/00; H03M13/27; H03M13/276; H03M13/2764; G; G11; G11B; G11B20/00; G11B20/10; G11B20/18; G11B20/1806; G11B20/1809; H03M13/2703
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
140 words
An interleaving circuit comprising: a memory area having (m x n) matrix blocks, a first address generator generating such first address sequence: where (Ri , C j ) is address of row i, column j of said memory area, a second address generator generating such second address sequence: where an interleaving circuit unit for interleaving; by memorizing product codes comprising a first code of code length m and a second code of code length n in said memory area by using said first address generator, by reading said memorized product codes by using said second address generator, thereby issuing record data, a de-interleaving circuit for de-interleaving; by memorizing demodulated data in said memory area by using said second address generator, and by reading said data memorized in the latest step, by using said first address generator, thereby issuing decoded data.
Claim 2
Dependent Claim
140 words
An interleaving circuit comprising: a memory area having (m x n) matrix blocks, a first address generator generating such first address sequence: where (Ri , C j ) is address of row i, column j of said memory area, a second address generator generating such second address sequence: where an interleaving circuit unit for interleaving; by memorizing product codes comprising a first code of code length m and a second code of code length n in said memory area by using said first address generator, by reading said memorized product codes by using said second address generator, thereby issuing record data, a de-interleaving circuit for de-interleaving; by memorizing demodulated data in said memory area by using said second address generator, and by reading said data memorized in the latest step, by using said first address generator, thereby issuing decoded data.
Claim 3
Dependent Claim
113 words
An interleaving circuit in accordance with claim 1, wherein said first and second address generators generate column address by multiplication of Golois field, said column address of (m x n) matrix memory area is represented by combination of non-zero elements in each Golois field, where each element α 1 , α 2 , ... α ℓ of different Golois fields are independent variable (wherein n = L 1 x L 2 x ... L ℓ and L 1 , L2 ···, L ℓ are each other prime, in case that L 1 , L 2 ..., L ℓ are order of each α 1 , α 2 , .... , α ℓ ).
Claim 4
Dependent Claim
27 words
Interleaving circuit in accordance with claim 2, wherein said second address generator generates column address of said second address sequence according to such producing rule of: where
Claim 5
Dependent Claim
105 words
Interleaving circuit in accordance with claim 1, wherein said column address of (m x n) matrix memory area is represented by combination of non-zero elements in each Golois field and combination of zero elements, where each element α 1 , α 2 , ..., α ℓ of different Golois fields are independent variable (wherein = L 1 x L 2 × ... x L ℓ +1 , L 1 , L 2 , ..., and L ℓ are relatively prime, provided that L 1 , L 2 , ..., L ℓ are order of each α 1 , α 2 , ..., α ℓ ).
Claim 6
Dependent Claim
28 words
Interleaving circuit in accordance with claim 4, wherein said second address generator generates column address of said second address sequence according to such producing rule of where and
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.