US5897359A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing a silicon/silicon germanium heterojunction bipolar transistor
Assignee: Electronics and Telecommunications Research Institute
•
Filing: 1997-12-09
•
Granted: 1999-04-27
•
Expires: 2017-12-09
Abstract
Abstract There is disclosed a method of manufacturing a silicon/silicon germanium heterojunction bipolar transistor having a good conformity and an improved speed characteristic, which includes the steps of sequentially laminating an underlying nitride film, an oxide film, a polycrystalline silicon film and an upper nitride on a semiconductor substrate on which devices are separated and a collector is formed; sequentially etching said upper nitride film and said polycrystalline silicon film using the emitter as a mask, and then forming a side wall nitride film; selectively wet-etching said oxide film to form a side base linker opening; burying said base linker opening with a polycrystalline silicon; oxidizing said polycrystalline silicon film buried into said base linker opening and then removing said oxide film by means of the selective wet-etch process; removing said upper nitride and then forming a silicon/silicon germanium film as a base film on the exposed thereof; and forming an emitter said silicon/silicon germanium film.
Inventors
- 👤 Deok Ho Cho
- 👤 Soo Min Lee
- 👤 Tae Hyeon Han
- 👤 Byung Ryul Ryum
- 👤 Kwang Eui Pyun
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 21:40
CPC Classifications
H; H10; H10D; H10D18/00; H10D10/00; H10D10/01; H10D10/021; H10D10/80; H10D10/821; H10D10/891
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
251 words
A method of manufacturing a silicon/silicon germanium heterojunction bipolar transistor, comprising the steps of: sequentially forming a first insulating film, a second insulating film, a first conductive layer, and a third insulating film on a semiconductor substrate on which devices are isolated and a collector is formed; sequentially etching said third insulating film and said first conductive layer using an emitter-opening mask, and then forming a first side wall insulating film on the etched surface thereof; wet-etching the exposed portion of said second insulating film, thereby forming a base linker opening; forming a second conductive layer on the entire structure in which said base linker opening is formed, thereby burying said base linker opening with said second conductive layer; oxidizing said second conductive layer to form an oxide film, with the portion of said second conductive layer buried into the base linker opening being unoxidized; removing said oxide film, thereby forming a base linker as the second conductive layer remained at said base linker opening; removing said first insulating film exposed by means of the base linker formation process; forming a silicon/silicon germanium film as a base film on the exposed surfaces of said base linker and said semiconductor substrate, thereby forming a base; forming a second side wall insulating film so as to cover said first side wall insulating film, and then forming an emitter as a third conductive layer on said silicon/silicon germanium film; and depositing a fourth insulating film, forming contact holes, and then performing a metal interconnections.
Claim 2
Independent Claim
251 words
A method of manufacturing a silicon/silicon germanium heterojunction bipolar transistor, comprising the steps of: sequentially forming a first insulating film, a second insulating film, a first conductive layer, and a third insulating film on a semiconductor substrate on which devices are isolated and a collector is formed; sequentially etching said third insulating film and said first conductive layer using an emitter-opening mask, and then forming a first side wall insulating film on the etched surface thereof; wet-etching the exposed portion of said second insulating film, thereby forming a base linker opening; forming a second conductive layer on the entire structure in which said base linker opening is formed, thereby burying said base linker opening with said second conductive layer; oxidizing said second conductive layer to form an oxide film, with the portion of said second conductive layer buried into the base linker opening being unoxidized; removing said oxide film, thereby forming a base linker as the second conductive layer remained at said base linker opening; removing said first insulating film exposed by means of the base linker formation process; forming a silicon/silicon germanium film as a base film on the exposed surfaces of said base linker and said semiconductor substrate, thereby forming a base; forming a second side wall insulating film so as to cover said first side wall insulating film, and then forming an emitter as a third conductive layer on said silicon/silicon germanium film; and depositing a fourth insulating film, forming contact holes, and then performing a metal interconnections.
Claim 3
Dependent Claim
29 words
A method of manufacturing a silicon/silicon germanium heterojunction bipolar transistor as claimed in claim 1, wherein said first insulating film and said third insulating film are formed of nitride.
Claim 4
Dependent Claim
43 words
A method of manufacturing a silicon/silicon germanium heterojunction bipolar transistor as claimed in claim 1, wherein said first insulating film is formed of a thickness of 5 nm-100 nm, and said third insulating film is formed of a thickness of 100 nm-500 nm.
Claim 5
Dependent Claim
24 words
A method of manufacturing a silicon/silicon germanium heterojunction bipolar transistor as claimed in claim 1, wherein said second insulating film is formed of oxide.
Claim 6
Dependent Claim
29 words
A method of manufacturing a silicon/silicon germanium heterojunction bipolar transistor as claimed in claim 1, wherein said second insulating film is formed of a thickness of 10 nm-500 nm.
Claim 7
Dependent Claim
30 words
A method of manufacturing a silicon/silicon germanium heterojunction bipolar transistor as claimed in claim 1, wherein said first conductive layer and said second conductive layer are P + crystalline silicon.
Claim 8
Dependent Claim
27 words
A method of manufacturing a silicon/silicon germanium heterojunction bipolar transistor as claimed in claim 1, wherein said third conductive layer is formed of N + polycrystalline silicon.
Claim 9
Dependent Claim
39 words
A method of manufacturing a silicon/silicon germanium heterojunction bipolar transistor as claimed in claim 1, wherein said first conductive layer and said second conductive layer are doped with boron in concentration of 10 18 -10 21 /cm 3 .
Claim 10
Dependent Claim
37 words
A method of manufacturing a silicon/silicon germanium heterojunction bipolar transistor as claimed in claim 1, wherein said first side wall insulating film is formed of nitride and said second side wall insulating film are formed of oxide.
Claim 11
Dependent Claim
30 words
A method of manufacturing a silicon/silicon germanium heterojunction bipolar transistor as claimed in claim 1, wherein said collector is doped in concentration of 10 18 -10 21 /cm 3 .
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-04-26 | 2002-10-26 | 2003-04-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-04-26 | 2006-10-26 | 2007-04-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-04-26 | 2010-10-26 | 2011-04-27 | $7700.00 | Window Closed / Lapsed |