Data output control circuit for semiconductor memory device

Claim 2

A data output control circuit for use in a semiconductor memory device, wherein input data is transmitted sequentially via a main amplifier controlled by an address transition detecting signal, a multiplex/latch unit, a data output buffer and an output operation device, the data output buffer comprising: an output control circuit that combines the address transition detecting signal, a control signal, and the input data to output first and second signals, wherein the output control circuit comprises, a first logic circuit that receives a first of the two input data, the address transition detecting signal and the control signal to output an intermediate control signal, a second logic circuit that receives the second of the two input data, the address transition detecting signal and the control signal to output the second signal, a high signal output circuit that receives the intermediate control signal to output a high level first signal, and a low signal output circuit that receives the second input data, the address transition detecting signal and the control signal to output a low level first signal.

Claim 3

The data output control circuit of claim 1, wherein the output control circuit prevents false data output during an interval for enabling the address transition detecting signal.

Claim 4

The data output control circuit of claim 1, wherein the output control circuit removes false data from a signal output by the output operation device.

Claim 5

The data output control circuit of claim 1, wherein the data output buffer prevents an interval for data reversal to improve data processing speed.

Claim 6

The data output control circuit of claim 1, wherein the address transition detecting signal is based on an address signal.

Claim 7

The data output control circuit of claim 1, wherein the control signal is a select signal based on the address transition detecting signal.

Claim 8

The data output control circuit as recited in claim 6, further comprising: a first NAND gate that receives the first input data, the address transition detecting signal and the select signal; a second NAND gate that receives the second input data, the address transition detecting signal and the select signal; first and second PMOS transistors having respective sources coupled to a supply potential, and wherein a gate of each of the first and second PMOS transistors is coupled to a corresponding drain of the other; a first NMOS transistor having a source coupled to ground, a gate coupled to an output of the first NAND gate and a drain coupled to the drain of the first PMOS transistor; second, third and fourth NMOS transistors serially coupled to each other between the drain of the second PMOS transistor and the ground, wherein the first input data, the select signal and the address transition detecting signal are respectively applied to gates of the second, third and fourth NMOS transistors; a node coupling the drain of the second PMOS transistor, a gate of the second NMOS transistor and a first input of the output operation device; and an output from the second NAND gate coupled to a second input of the output operation device.

Claim 9

The data output control circuit of claim 7, wherein the second input data is the inverse of the first input data.

Claim 10

The data output control circuit as recited in claim 1, further comprising: a first logic-gate that receives the first input data, the control signal and the address transition detecting signal; a second logic-gate that receives the second input data, the control signal and the address transition detecting signal; first and second transistors having respective sources coupled to a supply potential, and wherein a gate of each of the first and second transistors is coupled to a corresponding drain of the other; a third transistor having a source coupled to ground, a gate coupled to an output of the first logic-gate and a drain coupled to the drain of the first transistor; fourth, fifth and sixth transistors serially coupled to each other between the drain of the second transistor and the ground, wherein the first input data, the address transition detecting signal and the control signal are respectively applied to gates of the fourth, fifth and sixth transistors; a node coupling the drain of the second transistor, a gate of the fourth transistor and a first input of the output operation device; and an output from the second logic-gate coupled to a second input of the output operation device.

Claim 11

The data output control circuit as recited in claim 9, further comprising: a first logic gate that receives a first part of an input data, the address transition detecting signal and the select signal; a second logic gate that receives a second part of the input data, the address transition detecting signal and the select signal; first and second transistors of a first conductivity type having respective first electrodes coupled to a first potential, and wherein a control electrode of each of the first and second transistors is coupled to a corresponding second electrode of the other; a first transistor of a second conductivity type having a first electrode coupled to a second potential, a control electrode coupled to an output of the first logic gate and a second electrode coupled to the second electrode of the first transistor of the first conductivity type; second to fourth transistors of the second conductivity type serially coupled to each other between the second electrode of the second transistor of the first conductivity type and the second potential, wherein the first part of the input data, the select signal and the kill signal are respectively applied to control electrodes of the second to fourth transistors of the second conductivity type; a node coupling the second electrode of the second transistor of the first conductivity type, a control electrode of the second transistor of the second conductivity type and a first input of the output device; and an output from the second logic gate coupled to a second input of the output device.

Claim 12

The data output control circuit as recited in claim 10, wherein first and second logic gates are NAND gates, said first and second transistors of the first conductivity type are PMOS transistors and said first to fourth transistors of the second conductivity type are NMOS transistors, the first, second and control electrodes being source, drain and gate, respectively, and the first and second potentials being source and ground potentials, respectively.

Claim 13

The data output control circuit of claim 1, wherein the data output buffer operates in first and second modes, wherein in the first mode of the data output buffer the first and second signals are data signals, wherein in the second mode of the data output buffer, the first and second signals are non-data signals, and wherein the output operation device receives the first and second signals from the data output buffer to output one of two level data in the first mode and a third signal different from each of the two level data in the second mode.

Claim 14

A data output control circuit for a semiconductor memory device, comprising: a main amplifier that receives an address transition detecting signal for outputting data; a latch unit that latches the data received from the main amplifier; a data output buffer that combines the latched data from the latch unit, a control signal and the address transition detecting signal to output first and second signals; and an output device that receives the first and second signals from the data output buffer to output one of two level data in a data output state and a third signal different from each of the two level data in a suspended state.

Claim 15

A data output control circuit for a semiconductor memory device, comprising: a main amplifier that receives an address transition detecting signal for outputting data; a latch unit that latches the data received from the main amplifier; a data output buffer that combines the latched data from the latch unit, a control signal and the address transition detecting signal to output first and second signals; and an output device that receives the first and second signals from the data output buffer to output one of two level data in a data output state and a third signal different from each of the two level data in a suspended state.

Claim 16

The data output control circuit of claim 13, wherein the control signal is a select signal based on the address transition detecting signal.

Claim 17

The data output control circuit of claim 13, wherein the data output buffer causes the output device to generate a zero level signal when the address transition detecting signal is enabled.

Claim 18

The data output control circuit of claim 13, wherein the data output buffer prevents data reversal.

Claim 19

The data output control circuit of claim 13, wherein the data output buffer removes false data from a signal output by the output device.

Claim 20

The data output control circuit of claim 13, wherein the input data is for sequential transmission to an external circuit from the output device.

Claim 21

A data output control circuit for a semiconductor memory device, comprising: a main amplifier responsive to an address transition detecting signal to output data; a latch unit that latches the data received from the main amplifier; a data output buffer that combines the latched data from the latch unit, a control signal and the address transition detecting signal to output first and second signals, wherein the data output buffer operates in first and second states, wherein in the first state the first and second signals are data signals, and wherein in the second state the first and second signals are non-data signals; and an output device that receives the first and second signals from the data output buffer to output one of the two level data signals and a third signal different from each of the two level data.

Claim 22

A data output control circuit for a semiconductor memory device, comprising: a main amplifier responsive to an address transition detecting signal to output data; a latch unit that latches the data received from the main amplifier; a data output buffer that combines the latched data from the latch unit, a control signal and the address transition detecting signal to output first and second signals, wherein the data output buffer operates in first and second states, wherein in the first state the first and second signals are data signals, and wherein in the second state the first and second signals are non-data signals; and an output device that receives the first and second signals from the data output buffer to output one of the two level data signals and a third signal different from each of the two level data.