Semiconductor memory device comprising address transition detecting circuit having stable response characteristic for address signal conversion

Claim 2

A semiconductor memory device, comprising: a memory cell array including a plurality of memory cells being arranged in the form of a matrix; data read means selecting a corresponding one of said memory cells in response to an external address signal and starting a read operation in response to an address transition detecting signal having a prescribed pulse length; a plurality of address signal lines receiving said address signal and transmitting the same to said data read means; and address transition detecting means detecting a potential change of prescribed one of said address signal lines and outputting said address transition detecting signal, said address transition detecting means including: a plurality of signal change detecting means each outputting first and second detecting signals, being complementary to each other, being inverted in response to a potential change of a corresponding one of said prescribed address signal lines, a plurality of pulse generating means each outputting a pulse signal having said prescribed pulse length in response to inversion of corresponding said first and second detecting signals, and signal composing means outputting said address transition detecting signal having said prescribed pulse length in response to activation of any of said pulse signals from said plurality of pulse generating means, wherein each of said plurality of signal change detecting means comprises an inverter circuit and cross-coupled logic gates.

Claim 3

A semiconductor memory device, comprising: a memory cell array including a plurality of memory cells being arranged in the form of a matrix; data read means selecting a corresponding one of said memory cells in response to an external address signal and starting a read operation in response to an address transition detecting signal having a prescribed pulse length; a plurality of address signal lines receiving said address signal and transmitting the same to said data read means; and address transition detecting means detecting a potential change of prescribed one of said address signal lines and outputting said address transition detecting signal, said address transition detecting means including a plurality of signal change detecting means each outputting first and second detecting signals, being complementary to each other, being inverted in response to a potential change of a corresponding one of said prescribed address signal lines, a plurality of pulse generating means each outputting a pulse signal having said prescribed pulse length in response to inversion of corresponding said first and second detecting signals, and signal composing means outputting said address transition detecting signal having said prescribed pulse length in response to activation of any of said pulse signals from said plurality of pulse generating means, wherein each of said pulse generating means includes an output node outputting said pulse signal, discharge means discharging said output node in response to inversion of said first and second detecting signals being complementary to each other, delay switching means charging said output node in response to a lapse of a prescribed time often a potential change of said output node by said discharging, and latch means receiving a potential of said output node and holding said potential of said output node at said potential.

Claim 4

A semiconductor memory device, comprising: a memory cell array including a plurality of memory cells being arranged in the form of a matrix; data read means selecting a corresponding one of said memory cells in response to an external address signal and starting a read operation in response to an address transition detecting signal having a prescribed pulse length; a plurality of address signal lines receiving said address signal and transmitting the same to said data read means; and address transition detecting means detecting a potential change of prescribed one of said address signal lines and outputting said address transition detecting signal, said address transition detecting means including a plurality of signal change detecting means each outputting first and second detecting signals, being complementary to each other, being inverted in response to a potential change of a corresponding one of said prescribed address signal lines, a plurality of pulse generating means each outputting a pulse signal having said prescribed pulse length in response to inversion of corresponding said first and second detecting signals, and signal composing means outputting said address transition detecting signal having said prescribed pulse length in response to activation of any of said pulse signals from said plurality of pulse generating means, wherein each of said pulse generating means includes an output node outputting said pulse signal, discharge means discharging said output node in response to inversion of said first and second detecting signals being complementary to each other, delay switching means charging said output node in response to a lapse of a prescribed time often a potential change of said output node by said discharging, and latch means receiving a potential of said output node and holding said potential of said output node at said potential.

Claim 5

A semiconductor memory device, comprising: a memory cell array including a plurality of memory cells being arranged in the form of a matrix; data read means selecting a corresponding one of said memory cells in response to an external address signal and starting a read operation in response to an address transition detecting signal having a prescribed pulse length; a plurality of address signal lines receiving said address signal and transmitting the same to said data read means; and address transition detecting means detecting a potential change of prescribed one of said address signal lines and outputting said address transition detecting signal, said address transition detecting means including a plurality of signal change detecting means each outputting first and second detecting signals, being complementary to each other, being inverted in response to a potential change of a corresponding one of said prescribed address signal lines, a plurality of pulse generating means each outputting a pulse signal having said prescribed pulse length in response to inversion of corresponding said first and second detecting signals, and signal composing means outputting said address transition detecting signal having said prescribed pulse length in response to activation of any of said pulse signals from said plurality of pulse generating means, wherein each of said pulse generating means includes an output node outputting said pulse signal, first and second N-channel MOSFETs being connected between said output node and a first source potential, a first P-channel MOSFET having a drain being connected with said output node, second and third P-channel MOSFETs being connected in parallel between a source of said first P-channel MOSFET and a second source potential, signal delay means receiving a potential of said output node and outputting a corresponding potential to a gate of said first p-channel MOSFET after a lapse of a prescribed time, and latch means receiving said potential of said output node and holding said potential of said output node at said potential, said second N-channel MOSFET and said second P-channel MOSFET receive said first detecting signal in gates thereof, and said first N-channel MOSFET and said third P-channel MOSFET receive said second detecting signal in gates thereof.

Claim 6

A semiconductor memory device, comprising: a memory cell array including a plurality of memory cells being arranged in the form of a matrix; data read means selecting a corresponding one of said memory cells in response to an external address signal and starting a read operation in response to an address transition detecting signal having a prescribed pulse length; a plurality of address signal lines receiving said address signal and transmitting the same to said data read means; and address transition detecting means detecting a potential change of prescribed one of said address signal lines and outputting said address transition detecting signal, said address transition detecting means including a plurality of signal change detecting means each outputting first and second detecting signals, being complementary to each other, being inverted in response to a potential change of a corresponding one of said prescribed address signal lines, a plurality of pulse generating means each outputting a pulse signal having said prescribed pulse length in response to inversion of corresponding said first and second detecting signals, and signal composing means outputting said address transition detecting signal having said prescribed pulse length in response to activation of any of said pulse signals from said plurality of pulse generating means, wherein each of said pulse generating means includes an output node outputting said pulse signal, first and second N-channel MOSFETs being connected between said output node and a first source potential, a first P-channel MOSFET having a drain being connected with said output node, second and third P-channel MOSFETs being connected in parallel between a source of said first P-channel MOSFET and a second source potential, signal delay means receiving a potential of said output node and outputting a corresponding potential to a gate of said first p-channel MOSFET after a lapse of a prescribed time, and latch means receiving said potential of said output node and holding said potential of said output node at said potential, said second N-channel MOSFET and said second P-channel MOSFET receive said first detecting signal in gates thereof, and said first N-channel MOSFET and said third P-channel MOSFET receive said second detecting signal in gates thereof.

Claim 7

The semiconductor memory device according to claim 3, wherein each of said signal change detecting means includes: first and second internal output nodes outputting said first and second detecting signals respectively, third and fourth N-channel MOSFETs being connected in series between said first internal output node and said first source potential, fourth and fifth P-channel MOSFETs being connected in parallel between said first internal output node and said second source potential, fifth and sixth N-channel MOSFETs being connected in series between said second internal output node and said first source potential, sixth and seventh P-channel MOSFETs being connected in parallel between said second internal output node and said second source potential, and an inversion circuit receiving a potential of said address signal line and outputting inverted said potential, said third N-channel MOSFET and said fourth P-channel MOSFET receive said potential of said address signal line in gates thereof while said fifth N-channel MOSFET and said sixth P-channel MOSFET receive an output of said inversion circuit in gates thereof respectively, gates of said fourth N-channel MOSFET and said fifth P-channel MOSFET are connected with said second internal output node, and gates of said sixth N-channel MOSFET and said seventh P-channel MOSFET are connected with said first internal output node.

Claim 8

The semiconductor memory device according to claim 3, wherein said signal delay means includes: first odd stages of first cascade-connected inversion circuits receiving said potential of said output node, second odd stages of second cascade-connected inversion circuits receiving said potential of said output node, and a NOT-AND operation circuit receiving outputs of said first and second cascade-connected inversion circuits and having an output being connected with a gate of said first P-channel MOSFET.

Claim 9

The semiconductor memory device according to claim 5, wherein each of said signal change detecting means includes: first and second internal output nodes outputting said first and second detecting signals respectively, third and fourth N-channel MOSFETs being connected in series between said first internal output node and said first source potential, fourth and fifth P-channel MOSFETs being connected in parallel between said first internal output node and said second source potential, fifth and sixth N-channel MOSFETs being connected in series between said second internal output node and said first source potential, sixth and seventh P-channel MOSFETs being connected in parallel between said second internal output node and said second source potential, and an inversion circuit receiving a potential of said address signal line and outputting inverted said potential, said third N-channel MOSFET and said fourth P-channel MOSFET receive said potential of said address signal line in gates thereof while said fifth N-channel MOSFET and said sixth P-channel MOSFET receive an output of said inversion circuit in gates thereof respectively, gates of said fourth N-channel MOSFET and said fifth P-channel MOSFET are connected with said second internal output node, and gates of said sixth N-channel MOSFET and said seventh P-channel MOSFET are connected with said first internal output node.

Claim 10

The semiconductor memory device according to claim 1, wherein an input of the inverter circuit is connected to a corresponding one of said plurality of address signal lines and an output of said inverter circuit is connected to an input of one of said cross-coupled logic gates, an input of another cross-coupled logic gates is connected to said corresponding one of said plurality of address signal lines, and said cross-coupled logic gates output said first and second detecting signals.