Semiconductor memory device having hierarchy control circuit architecture of master/local control circuits permitting high speed accessing

Claim 2

A semiconductor memory device, comprising: a plurality of memory mats each having a plurality of memory cells arranged in rows and columns; a master control circuit coupled to receive and responsive to an externally applied signal including an address signal, for generating an internal address signal and an internal control signal commonly to said plurality of memory mats; a plurality of local control circuits provided corresponding to each of the memory mats for controlling accessing to memory cells in corresponding memory mats based on the internal address signal and the internal control signal from said master control circuit; and buffer means provided between said master control circuit and each of the local control circuits for buffering a signal received from said master control circuit for transmission to each of said plurality of local control circuits.

Claim 3

The semiconductor memory device as recited in claim 1, wherein said semiconductor memory device is formed on a rectangular semiconductor chip having a first side and a second side longer than said first side, and wherein said plurality of local control circuits each include a sub local control circuit provided for a corresponding memory mat and in parallel with said first side, an output signal from said master control circuit is transmitted along an extending direction of said second side, and said buffer means includes a buffer circuit receiving a signal transmitted from said master control circuit along the direction of said second side for buffering the received signal for transmission to each said sub local control circuit along an extending direction of said first side.

Claim 4

The semiconductor memory device as recited in claim 2, wherein each of the memory mats is divided into a plurality of arrays along the direction of said second side, and said sub local control circuit is provided along the direction of said first side between adjacent arrays in a corresponding memory mat.

Claim 5

The semiconductor memory device as recited in claim 3, wherein each of the memory mats is divided into two arrays.

Claim 6

The semiconductor memory device as recited in claim 3, wherein each of the memory mats is divided into first to fourth four adjacent arrays, and said sub local control circuit is provided between said first and second arrays and between said third and fourth arrays in a corresponding memory mat.

Claim 7

The semiconductor memory device as recited in claim 2, wherein said sub local control circuit includes a row related circuit associated with a row selection to drive an addressed row of memory cells in a corresponding memory mat into a selected state.

Claim 8

The semiconductor memory device as recited in claim 2, wherein each said local control circuit further includes a column related circuit provided along the direction of said second side in a corresponding memory mat for selecting an addressed column of memory cells in said corresponding memory mat.

Claim 9

The semiconductor memory device as recited in claim 7, wherein said buffer means further includes a buffer provided corresponding to each of the memory mats for buffering a signal received from said master control circuit and transmitting the buffered signal in opposite directions from each other along the direction of said second side for application to a corresponding column related circuit.

Claim 10

A semiconductor memory device formed on a rectangular semiconductor chip having a first side and a second side longer than said first side, comprising: a plurality of memory mats, each having a shorter side in the first side direction and a longer side in the second side direction longer than said shorter side and having a plurality of memory cells arranged in rows and columns, said plurality of memory mats being provided in four regions of said rectangular semiconductor chip, respectively, said semiconductor chip being divided by a central portion in each of the first and second sides into said four regions; row selecting means provided along said shorter side of each respective memory mat for driving a row addressed by a first address signal into a selected state in a corresponding memory mat, and column selecting means provided along said longer side of each respective memory mat for selecting a column addressed by a second address signal in a corresponding memory mat.

Claim 11

A semiconductor memory device formed on a rectangular semiconductor chip having a first side and a second side longer than said first side, comprising: a plurality of memory mats, each having a shorter side in the first side direction and a longer side in the second side direction longer than said shorter side and having a plurality of memory cells arranged in rows and columns, said plurality of memory mats being provided in four regions of said rectangular semiconductor chip, respectively, said semiconductor chip being divided by a central portion in each of the first and second sides into said four regions; row selecting means provided along said shorter side of each respective memory mat for driving a row addressed by a first address signal into a selected state in a corresponding memory mat, and column selecting means provided along said longer side of each respective memory mat for selecting a column addressed by a second address signal in a corresponding memory mat.

Claim 12

The semiconductor memory device as recited in claim 9, wherein said column selecting means is provided in a corresponding memory mat facing the central portion for said first side.

Claim 13

A semiconductor memory device formed on a rectangular semiconductor chip having a first side and a second side longer that said first side, said semiconductor memory device comprising: a plurality of memory mats, each having a shorter side in the first side direction and a longer side in the second side direction longer than said shorter side and having a plurality of memory cells arranged in rows and columns, said plurality of memory mats being provided in four regions of said rectangular semiconductor chip, respectively, said semiconductor chip being divided by a central portion in each of the first and second sides into said four regions; row selecting means provided alone said shorter side of each of said memory mats for providing a row addressed by a first address signal into a selected state; column selecting means provided in a corresponding memory mat along said longer side of said corresponding memory mat and facing the central portion for said first side for selecting a column addressed by a second address signal; a master control circuit provided in a central region for both said first and second sides of said semiconductor chip for generating an internal signal commonly to the memory mat in each of the four regions in accordance with an externally applied signal including an address signal and transmitting the generated signal through the central portion for said first side along said second side direction, and buffer means provided corresponding to each of the memory mats for buffering the signal received from said master control circuit and transmitting the buffered signal to the row selecting means in corresponding memory mat.

Claim 14

A semiconductor memory device formed on a rectangular semiconductor chip having a first side and a second side longer that said first side, said semiconductor memory device comprising: a plurality of memory mats, each having a shorter side in the first side direction and a longer side in the second side direction longer than said shorter side and having a plurality of memory cells arranged in rows and columns, said plurality of memory mats being provided in four regions of said rectangular semiconductor chip, respectively, said semiconductor chip being divided by a central portion in each of the first and second sides into said four regions; row selecting means provided alone said shorter side of each of said memory mats for providing a row addressed by a first address signal into a selected state; column selecting means provided in a corresponding memory mat along said longer side of said corresponding memory mat and facing the central portion for said first side for selecting a column addressed by a second address signal; a master control circuit provided in a central region for both said first and second sides of said semiconductor chip for generating an internal signal commonly to the memory mat in each of the four regions in accordance with an externally applied signal including an address signal and transmitting the generated signal through the central portion for said first side along said second side direction, and buffer means provided corresponding to each of the memory mats for buffering the signal received from said master control circuit and transmitting the buffered signal to the row selecting means in corresponding memory mat.

Claim 15

The semiconductor memory device as recited in claim 10, wherein each of the memory mats is divided in said second side direction into a plurality of arrays each having a plurality of memory cells arranged in rows and columns, and said row selecting means is provided between adjacent arrays in a corresponding memory mat.

Claim 16

The semiconductor memory device as recited in claim 12, wherein each of the memory mats is divided into two arrays.

Claim 17

The semiconductor memory device as recited in claim 12, wherein each of the memory mats is divided into first to fourth arrays along said second side direction, and said row selecting means is provided between said first and second arrays and between said third and fourth arrays.

Claim 18

The semiconductor memory device as recited in claim 11, further comprising column buffer means provided corresponding to each of the memory mats for buffering a signal associated with a column selection from said master control circuit for transmission to column selecting means in a corresponding memory mat.

Claim 19

The semiconductor memory device as recited in claim 15, wherein said column buffer means includes means provided in a central portion with respect to said second side direction in a corresponding memory mat for transmitting a buffered signal in opposite directions to each other.

Claim 20

The semiconductor memory device as recited in claim 11, wherein said master control circuit includes predecode means provided corresponding to the memory mats for predecoding an internal address signal generated in said master control circuit and transmitting the predecoded signal to said buffer means along said second side direction.

Claim 21

The semiconductor memory device as recited in claim 15, wherein said master control circuit includes predecode means provided for the memory mats for predecoding an internal address signal generated in said master control circuit in accordance with said address signal for transmission to the column buffer means along the second side direction.

Claim 22

The semiconductor memory device according to claim 1, wherein said buffer means comprises a drive circuit receiving the signal from the master control circuit for driving an output node thereof to a voltage level corresponding to the received signal.

Claim 23

The semiconductor memory device according to claim 1, wherein the signal from the master control circuit is at least one of said internal address signal and said internal control signal.