US5477488A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System, a memory and a process having bit processing circuits associated with memory for pre-processing data read by a processor
Assignee: Texas Instruments Inc
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Filing: 1994-02-14
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Granted: 1995-12-19
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Expires: 2014-02-14
Abstract
Abstract Bit processing circuits 100,102 and 104 on the substrate of memory circuits 24 perform bit operations on the data read from addressable storage locations 86 before producing the bit processed data from the memory. A system includes central processing unit circuits 22 on a substrate separate from the memory 24 and producing bit operation information in time multiplexed sequence on the address leads 32 or to normally not-connected leads (NC) on the memory substrate.
Inventors
- 👤 K. Subramani
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 23:00
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1006
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
141 words
A computer system comprising: A. central processing unit circuits formed on a substrate, the central processing unit circuits asserting data, address information and bit operation information and receiving bit processed data; and B. memory circuits formed on at least one substrate separate from the substrate of the central processing unit circuits, the memory circuits having terminals coupled to the data, address information and bit operation information of the central processing unit circuits and having an array of addressable locations for storing data, the memory circuits also having a data path extending between the terminals and the array and the memory circuits conveying data over the data path in response to the address signals, the memory circuits including operation circuits connected to the data path for operating on the data in response to the bit operation information from the central processing unit.
Claim 2
Dependent Claim
141 words
A computer system comprising: A. central processing unit circuits formed on a substrate, the central processing unit circuits asserting data, address information and bit operation information and receiving bit processed data; and B. memory circuits formed on at least one substrate separate from the substrate of the central processing unit circuits, the memory circuits having terminals coupled to the data, address information and bit operation information of the central processing unit circuits and having an array of addressable locations for storing data, the memory circuits also having a data path extending between the terminals and the array and the memory circuits conveying data over the data path in response to the address signals, the memory circuits including operation circuits connected to the data path for operating on the data in response to the bit operation information from the central processing unit.
Claim 3
Dependent Claim
27 words
The system of claim 1 in which the central processing unit circuits produce the bit operation information in time multiplexed sequence with the data and address information.
Claim 4
Dependent Claim
20 words
The system of claim 1 in which the memory circuits include normally not-connected leads that receive the bit operation information.
Claim 5
Dependent Claim
100 words
A memory device comprising: A. a substrate; B. input terminals on the substrate for receiving address information and data operation information; C. at least one array of storage locations on the substrate for storing data at certain addressable locations indicated by the address information; D. data terminals on the substrate for conveying data to and from the substrate; E. a data path extending and conveying data between the data terminals and the at least one array of storage locations; and F. operation circuits for processing the data conveyed on the data path in response to the received data operation information.
Claim 6
Dependent Claim
100 words
A memory device comprising: A. a substrate; B. input terminals on the substrate for receiving address information and data operation information; C. at least one array of storage locations on the substrate for storing data at certain addressable locations indicated by the address information; D. data terminals on the substrate for conveying data to and from the substrate; E. a data path extending and conveying data between the data terminals and the at least one array of storage locations; and F. operation circuits for processing the data conveyed on the data path in response to the received data operation information.
Claim 7
Dependent Claim
23 words
The memory of claim 4 in which the input terminals receive the address information and the data operation information in time multiplexed sequence.
Claim 8
Dependent Claim
19 words
The memory of claim 4 in which the input terminals receive the data operation information on normally not-connected terminals.
Claim 9
Dependent Claim
80 words
A process of conveying data in a memory device, comprising: A. providing a semiconductor substrate having terminals for receiving address information, for sending and receiving data and for receiving data operation information, the substrate also having addressable storage locations containing data; B. conveying data between the addressable storage locations and substrate terminals in response to the address information; and C. processing the conveyed data between the addressable storage locations and the substrate terminals in response to the data operation information.
Claim 10
Dependent Claim
80 words
A process of conveying data in a memory device, comprising: A. providing a semiconductor substrate having terminals for receiving address information, for sending and receiving data and for receiving data operation information, the substrate also having addressable storage locations containing data; B. conveying data between the addressable storage locations and substrate terminals in response to the address information; and C. processing the conveyed data between the addressable storage locations and the substrate terminals in response to the data operation information.
Claim 11
Dependent Claim
16 words
The process of claim 7 in which the conveying includes reading data from the addressable locations.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-12-18 | 1999-06-19 | 1999-12-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-12-18 | 2003-06-19 | 2003-12-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-12-18 | 2007-06-19 | 2007-12-19 | $7700.00 | Window Closed / Lapsed |