Sense amplifiers including bipolar transistor input buffers and field effect transistor latch circuits

Claim 2

A sense amplifier for an integrated circuit memory device comprising: a bipolar transistor voltage gain input buffer that is responsive to a pair of complementary input signals from a memory cell, to amplify the voltage differential between the pair of complementary input signals; and a field effect transistor latch circuit that is responsive to the bipolar transistor voltage gain input buffer, to latch the voltage differential so amplified and thereby produce a pair of complementary output signals.

Claim 3

A sense amplifier according to claim 1: wherein the bipolar transistor voltage gain input buffer comprises a differential pair of bipolar transistors; and wherein the field effect transistor latch circuit comprises a cross-coupled pair of field effect transistors.

Claim 4

A sense amplifier according to claim 2; wherein the bipolar transistor voltage gain input buffer further comprises a field effect transistor constant current source that supplies constant current to the differential pair of bipolar transistors; wherein the cross coupled pair of field effect transistors are of first conductivity type; and wherein the field effect transistor latch circuit further comprises a second pair of field effect transistors of second conductivity type, a respective one of which is coupled between a respective one of the differential pair of bipolar transistors and a respective one of the cross-coupled pair of field effect transistors.

Claim 5

A sense amplifier according to claim 3 wherein the bipolar transistor voltage gain input buffer further comprises a pair of field effect transistor load transistors, a respective one of which is coupled to a respective one of the differential pair of bipolar transistors.

Claim 6

A sense amplifier for an integrated circuit memory device, comprising: first and second field effect transistors that are serially connected to define a first output node therebetween; third and fourth field effect transistors that are serially connected to define a second output node therebetween; first and second bipolar transistors each having a base, an emitter and a collector, the emitters of the first and second bipolar transistors being commonly connected, the respective bases of the first and second bipolar transistors being connected to respective first and second complementary input signals from a memory cell; each of the first through fourth field effect transistors including a gate, the collector of the first bipolar transistor being connected to the gate of the second field effect transistor, the collector of the second bipolar transistor being connected to the gate of the fourth field effect transistor, the gate of the first field effect transistor being connected to the second output node and the gate of the third field effect transistor being connected to the first output node.

Claim 7

A sense amplifier for an integrated circuit memory device, comprising: first and second field effect transistors that are serially connected to define a first output node therebetween; third and fourth field effect transistors that are serially connected to define a second output node therebetween; first and second bipolar transistors each having a base, an emitter and a collector, the emitters of the first and second bipolar transistors being commonly connected, the respective bases of the first and second bipolar transistors being connected to respective first and second complementary input signals from a memory cell; each of the first through fourth field effect transistors including a gate, the collector of the first bipolar transistor being connected to the gate of the second field effect transistor, the collector of the second bipolar transistor being connected to the gate of the fourth field effect transistor, the gate of the first field effect transistor being connected to the second output node and the gate of the third field effect transistor being connected to the first output node.

Claim 8

A sense amplifier according to claim 5 wherein the first and third field effect transistors are of first conductivity type and wherein the second and fourth field effect transistors are of second conductivity type.

Claim 9

A sense amplifier according to claim 5 further comprising: fifth and sixth field effect transistors, the first, second and fifth field effect transistors being serially connected between first and second reference voltages and the third, fourth and sixth field effect transistors being serially connected between the first and second reference voltages; the fifth and sixth field effect transistors each including a gate that is connected to an enable signal.

Claim 10

A sense amplifier according to claim 7 wherein the first and third field effect transistors are of first conductivity type and wherein the second, fourth, fifth and sixth field effect transistors are of second conductivity type.

Claim 11

A sense amplifier according to claim 5 further comprising: seventh and eighth field effect transistors, a respective one of which is serially connected between the first reference voltage and a respective collector of the first and second bipolar transistors.

Claim 12

A sense amplifier according to claim 5 further comprising a ninth field effect transistor connected between the commonly connected emitters of the first and second bipolar transistors and the second reference voltage.

Claim 13

A sense amplifier according to claim 9 further comprising a ninth field effect transistor connected between the commonly connected emitters of the first and second bipolar transistors and the second reference voltage.

Claim 14

A sense amplifier according to claim 9 wherein the first, third, seventh and eighth field effect transistors are of first conductivity type and wherein the second, fourth, fifth and sixth field effect transistors are of second conductivity type.

Claim 15

A sense amplifier according to claim 11 wherein the first, third, seventh and eighth field effect transistors are of first conductivity type and wherein the second, fourth, fifth, sixth and ninth field effect transistors are of second conductivity type.

Claim 16

A sense amplifier according to claim 7 further comprising: seventh and eighth field effect transistors, a respective one of which is serially connected between the first reference voltage and a respective collector of the first and second bipolar transistors.

Claim 17

A sense amplifier according to claim 7 further comprising a ninth field effect transistor connected between the commonly connected emitters of the first and second bipolar transistors and the second reference voltage.

Claim 18

A sense amplifier according to claim 14 further comprising a ninth field effect transistor connected between the commonly connected emitters of the first and second bipolar transistors and the second reference voltage.

Claim 19

A sense amplifier according to claim 15 wherein the first, third, seventh and eighth field effect transistors are of first conductivity type and wherein the second, fourth, fifth and sixth field effect transistors are of second conductivity type.

Claim 20

A sense amplifier according to claim 16 wherein the first, third, seventh and eighth field effect transistors are of first conductivity type and wherein the second, fourth, fifth, sixth and ninth field effect transistors are of second conductivity type.

Claim 21

A sense amplifier for an integrated circuit memory device comprising: a transistor input buffer that is responsive to a pair of complementary input signals from a memory cell, to amplify the voltage differential between the pair of complementary input signals; and a transistor latch circuit that is responsive to the transistor input buffer, to latch the voltage differential so amplified and thereby produce a pair of complementary output signals; the transistor input buffer including transistors having smaller threshold variation than the transistor latch circuit.

Claim 22

A sense amplifier for an integrated circuit memory device comprising: a transistor input buffer that is responsive to a pair of complementary input signals from a memory cell, to amplify the voltage differential between the pair of complementary input signals; and a transistor latch circuit that is responsive to the transistor input buffer, to latch the voltage differential so amplified and thereby produce a pair of complementary output signals; the transistor input buffer including transistors having smaller threshold variation than the transistor latch circuit.

Claim 23

A sense amplifier according to claim 19: wherein the transistor input buffer comprises a differential pair of bipolar transistors; and wherein the transistor latch circuit comprises a cross-coupled pair of field effect transistors.