Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
104 words
A CMOS passive pixel sensor system, comprising: a pixel comprising a photodetector connected to an access transistor; a capacitive transimpedance amplifier (CTIA) having a CTIA input and a CTIA output; an electrical bus connecting said pixel to said CTIA input; a reset switch and a selectable feedback capacitance connected in parallel from said CTIA input to said CTIA output; a selectable load capacitance connected to said CTIA output; a first correlated double sampling circuit connected to said load capacitance; a sample-and-hold buffer circuit connected to said first correlated double sampling circuit; and an offset cancellation circuit connecting said buffer circuit to an output bus.
Claim 2
Dependent Claim
104 words
A CMOS passive pixel sensor system, comprising: a pixel comprising a photodetector connected to an access transistor; a capacitive transimpedance amplifier (CTIA) having a CTIA input and a CTIA output; an electrical bus connecting said pixel to said CTIA input; a reset switch and a selectable feedback capacitance connected in parallel from said CTIA input to said CTIA output; a selectable load capacitance connected to said CTIA output; a first correlated double sampling circuit connected to said load capacitance; a sample-and-hold buffer circuit connected to said first correlated double sampling circuit; and an offset cancellation circuit connecting said buffer circuit to an output bus.
Claim 3
Dependent Claim
30 words
The CMOS passive pixel sensor system of claim 1, wherein said pixel further comprises an overflow transistor connected to said photodetector and having a gate continually biased for preventing saturation.
Claim 4
Dependent Claim
26 words
The CMOS passive pixel sensor system of claim 2, wherein said photodetector comprises a photodiode formed from a lightly doped source region of said access transistor.
Claim 5
Dependent Claim
24 words
The CMOS passive pixel sensor system of claim 1, wherein said capacitive transimpedance amplifier (CTIA) includes a high gain, wide bandwidth, CMOS differential amplifier.
Claim 6
Dependent Claim
33 words
The CMOS passive pixel sensor system of claim 4, wherein said CMOS differential amplifier has a first input connected to said CTIA input and a second input connected to a low noise reference.
Claim 7
Dependent Claim
35 words
The CMOS passive pixel sensor system of claim 5, wherein said second input of said CMOS differential amplifier is connected to a black pixel that generates said low noise reference for subtracting fixed pattern noise.
Claim 8
Dependent Claim
32 words
The CMOS passive pixel sensor system of claim 1, further comprising a pipeline circuit having at least first and second parallel paths connected between said buffer circuit and said offset cancellation circuit.
Claim 9
Dependent Claim
27 words
The CMOS passive pixel sensor system of claim 1, further comprising a second correlated double sampling circuit connected between said buffer circuit and said offset cancellation circuit.
Claim 10
Dependent Claim
37 words
The CMOS passive pixel sensor system of claim 8, wherein said offset cancellation circuit includes an output amplifier having an input connected to said second correlated double sampling circuit and an output connected to said output bus.
Claim 11
Dependent Claim
39 words
The CMOS passive pixel sensor system of claim 9, wherein said offset cancellation circuit further includes a low transconductance amplifier having an input connected to a low spatial noise reference signal and an output connected to said output bus.
Claim 12
Dependent Claim
153 words
A readout circuit for a CMOS passive pixel sensor system, comprising: a plurality of pixels connected to an input bus, each of said pixels comprising a photodetector, an overflow transistor connected to said photodetector, and an access transistor connecting said photodetector to said input bus; a high gain, wide bandwidth, CMOS differential amplifier having a first input connected to said input bus, a second input connected to a low noise reference, and an amplifier output; a reset switch and a feedback capacitance connected in parallel from said input bus to said amplifier output; a selectable load capacitance connected to said amplifier output; a first correlated double sampling circuit connected to said load capacitance; a sample-and-hold buffer circuit connected to said first correlated double sampling circuit; an offset cancellation circuit connected to an output bus; and a pipeline circuit having at least two parallel branches connecting said buffer circuit to said offset cancellation circuit.
Claim 13
Dependent Claim
153 words
A readout circuit for a CMOS passive pixel sensor system, comprising: a plurality of pixels connected to an input bus, each of said pixels comprising a photodetector, an overflow transistor connected to said photodetector, and an access transistor connecting said photodetector to said input bus; a high gain, wide bandwidth, CMOS differential amplifier having a first input connected to said input bus, a second input connected to a low noise reference, and an amplifier output; a reset switch and a feedback capacitance connected in parallel from said input bus to said amplifier output; a selectable load capacitance connected to said amplifier output; a first correlated double sampling circuit connected to said load capacitance; a sample-and-hold buffer circuit connected to said first correlated double sampling circuit; an offset cancellation circuit connected to an output bus; and a pipeline circuit having at least two parallel branches connecting said buffer circuit to said offset cancellation circuit.
Claim 14
Dependent Claim
28 words
The readout circuit of claim 11, wherein said feedback capacitance comprises a plurality of selectable feedback capacitors connected in parallel from said input bus to said amplifier output.
Claim 15
Dependent Claim
23 words
The readout circuit of claim 11, wherein each of said parallel branches of said pipeline circuit includes a second correlated double sampling circuit.
Claim 16
Dependent Claim
55 words
The readout circuit of claim 11, wherein said offset cancellation circuit comprises: an output amplifier having an input connected to said pipeline circuit and an output connected to said output bus; and a low transconductance amplifier having an input connected to a low spatial noise reference signal and an output connected to said output bus.
Claim 17
Dependent Claim
32 words
The readout circuit of claim 11, wherein said second input of said CMOS differential amplifier is connected to a black pixel that generates said low noise reference for subtracting fixed pattern noise.
Claim 18
Dependent Claim
194 words
A CMOS column readout circuit for an array of passive pixels, comprising: a column bus connecting a column of said pixels to the readout circuit; each of said column pixels comprising an access transistor connected to said column bus, a lightly doped source region of said access transistor forming a photodiode, and an overflow transistor connected to said photodiode; a capacitive transimpedance amplifier (CTIA) comprising a high gain, wide bandwidth, CMOS differential amplifier having a first input connected to said column bus, a second input connected to a low noise reference, and an amplifier output; said CTIA including a reset switch and a selectable feedback capacitance connected in parallel between said first amplifier input and said amplifier output; a selectable load capacitance connected to said amplifier output; a first correlated double sampling circuit connected to said load capacitance; a sample-and-hold buffer circuit connected to said first correlated double sampling circuit; an offset cancellation circuit connected to an output bus; and a pipeline circuit having at least two parallel branches connecting said buffer circuit to said offset cancellation circuit, each of said parallel branches of said pipeline circuit includes a second correlated double sampling circuit.
Claim 19
Dependent Claim
194 words
A CMOS column readout circuit for an array of passive pixels, comprising: a column bus connecting a column of said pixels to the readout circuit; each of said column pixels comprising an access transistor connected to said column bus, a lightly doped source region of said access transistor forming a photodiode, and an overflow transistor connected to said photodiode; a capacitive transimpedance amplifier (CTIA) comprising a high gain, wide bandwidth, CMOS differential amplifier having a first input connected to said column bus, a second input connected to a low noise reference, and an amplifier output; said CTIA including a reset switch and a selectable feedback capacitance connected in parallel between said first amplifier input and said amplifier output; a selectable load capacitance connected to said amplifier output; a first correlated double sampling circuit connected to said load capacitance; a sample-and-hold buffer circuit connected to said first correlated double sampling circuit; an offset cancellation circuit connected to an output bus; and a pipeline circuit having at least two parallel branches connecting said buffer circuit to said offset cancellation circuit, each of said parallel branches of said pipeline circuit includes a second correlated double sampling circuit.
Claim 20
Dependent Claim
34 words
The CMOS column readout circuit of claim 16, wherein said second input of said CMOS differential amplifier is connected to a black pixel that generates said low noise reference for subtracting fixed pattern noise.
Claim 21
Dependent Claim
33 words
The CMOS column readout circuit of claim 16, wherein said offset cancellation circuit includes an output amplifier having an input connected to said pipeline circuit and an output connected to said output bus.
Claim 22
Dependent Claim
37 words
The CMOS column readout circuit of claim 18, wherein said offset cancellation circuit further includes a low transconductance amplifier having an input connected to a low spatial noise reference and an output connected to said output bus.
Claim 23
Dependent Claim
25 words
The CMOS column readout circuit of claim 16, further comprising digital logic for reading out selected ones of said pixels connected to said column bus.