Patent US5891775A successfully refreshed from Google Patents.
US5891775A
Expired / Lapsed
US
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Method of making nonvolatile semiconductor device having sidewall split gate for compensating for over-erasing operation
Assignee: NEC Corp
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Filing: 1997-06-24
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Granted: 1999-04-06
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Expires: 2017-06-24
Abstract
Abstract In a nonvolatile semiconductor memory device, including a semiconductor substrate, a floating gate formed over the semiconductor substrate, and a control gate formed over the floating gate, a split gate is formed on a sidewall of the control gate and the floating gate and is electrically connected to the control gate. A source region and a drain region are formed in the semiconductor substrate on the sides of the control gate and the split gate.
Inventors
- 👤 Yosiaki Hisamune
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 04:53
CPC Classifications
H; H10; H10B; H10B69/00; H10B10/00; H10B41/00; H10B41/30
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
345 words
A method for manufacturing a nonvolatile semiconductor memory device, comprising the steps of: forming a first insulating layer (3) formed on a semiconductor substrate (1) of a first conductivity type; forming a first conductive layer (4) on said first insulating layer; forming a second insulating layer (5) on said first conductive layer; forming a second conductive layer (6) on a second insulating layer; patterning said second conductive layer, said second insulating layer, said first conductive layer and said first insulating layer, to form a first control gate pattern made of said second conductive layer and a first floating gate pattern made of said first conductive layer in parallel with a first direction; forming a third insulating layer (7) on said first control gate pattern and said first floating gate pattern; forming a third conductive layer (8) on said third conductive layer; etching back said third conductive layer to form first split gate patterns on both sidewalls of said first control gate pattern and said first floating gate pattern; removing one of said first split gate patterns on one of said sidewalls of said first control gate pattern and said first floating gate pattern; introducing impurities of a second conductivity type opposite to said first conductivity type into said semiconductor substrate with a mask of said first control gate pattern and said split gate pattern to form source and drain regions (1) in said semiconductor substrate; forming a fourth conductive layer (22) on said first control pattern and said first split gate pattern; patterning said fourth conductive layer, said first control gate pattern and said first floating gate pattern to form a word line made of said fourth conductive layer, a second control gate pattern made of said first control gate pattern, a second floating gate pattern made of said first floating gate pattern, and a second split gate pattern made of said first split gate pattern in parallel with a second direction opposite to said first direction, said second split gate pattern being electrically connected via said word line to said second control gate pattern.
Claim 2
Independent Claim
345 words
A method for manufacturing a nonvolatile semiconductor memory device, comprising the steps of: forming a first insulating layer (3) formed on a semiconductor substrate (1) of a first conductivity type; forming a first conductive layer (4) on said first insulating layer; forming a second insulating layer (5) on said first conductive layer; forming a second conductive layer (6) on a second insulating layer; patterning said second conductive layer, said second insulating layer, said first conductive layer and said first insulating layer, to form a first control gate pattern made of said second conductive layer and a first floating gate pattern made of said first conductive layer in parallel with a first direction; forming a third insulating layer (7) on said first control gate pattern and said first floating gate pattern; forming a third conductive layer (8) on said third conductive layer; etching back said third conductive layer to form first split gate patterns on both sidewalls of said first control gate pattern and said first floating gate pattern; removing one of said first split gate patterns on one of said sidewalls of said first control gate pattern and said first floating gate pattern; introducing impurities of a second conductivity type opposite to said first conductivity type into said semiconductor substrate with a mask of said first control gate pattern and said split gate pattern to form source and drain regions (1) in said semiconductor substrate; forming a fourth conductive layer (22) on said first control pattern and said first split gate pattern; patterning said fourth conductive layer, said first control gate pattern and said first floating gate pattern to form a word line made of said fourth conductive layer, a second control gate pattern made of said first control gate pattern, a second floating gate pattern made of said first floating gate pattern, and a second split gate pattern made of said first split gate pattern in parallel with a second direction opposite to said first direction, said second split gate pattern being electrically connected via said word line to said second control gate pattern.
Claim 3
Dependent Claim
32 words
A method as set forth in claim 1, further comprising a step of fitting an insulating layer (21) on said source and drain regions before the formation of said fourth conductive layer.
Claim 4
Dependent Claim
57 words
A method as set forth in claim 1, wherein said step of forming a first insulating layer (3) forms a silicon oxide layer by thermally oxidizing a p- type monocrystalline silicon substrate (1) having a concentration of about 2×10 15 borons/cm 3 , said first insulating layer (3) having a thickness between about 7 and 10 nanometers.
Claim 5
Dependent Claim
36 words
A method as set forth in claim 1, wherein said step of forming a first conductive layer (4) includes the steps of depositing a polycrystalline silicon layer by a CVD process and doping phosphorous ions thereinto.
Claim 6
Dependent Claim
42 words
A method as set forth in claim 1, wherein said step of forming a second insulating layer (5) includes the step of forming a laminated configuration of silicon oxide, silicon nitride and silicon oxide (ONO) deposited using a low temperature CVD process.
Claim 7
Dependent Claim
36 words
A method as set forth in claim 5, wherein in the step of forming a second insulating layer (5), the silicon oxide layer of the second insulating layer (5) has a thickness of about 20 nanometers.
Claim 8
Dependent Claim
36 words
A method as set forth in claim 1, wherein said step of forming a second conductive layer (6) forms a layer of polycrystalline silicon and metal silicide deposited by a CVD process and a sputtering process.
Claim 9
Dependent Claim
33 words
A method as set forth in claim 1, wherein said step of forming a second conductive layer (6) forms a layer of polycrystalline silicon deposited by a CVD process and a sputtering process.
Claim 10
Dependent Claim
54 words
A method as set forth in claim 1, wherein said step of patterning said second conductive layer, said second insulating layer, said first conductive layer and said first insulating layer is performed using a photolithography and etching process to form the first control gate pattern and the first floating gate pattern in self alignment.
Claim 11
Dependent Claim
37 words
A method as set forth in claim 1, wherein said step of forming a third insulating layer (7) forms a silicon oxide layer with a thickness between about 0.1 and 0.5 micrometers deposited using a CVD process.
Claim 12
Dependent Claim
35 words
A method as set forth in claim 1, wherein said step of forming a third conductive layer (8) forms a polycrystalline silicon layer with a thickness of about 0.25 micrometers deposited using a CVD process.
Claim 13
Dependent Claim
61 words
A method as set forth in claim 1, wherein said step of removing one of said first split gate patterns includes the steps of: forming a photoresist pattern (10) to cover a portion of the split gate pattern; removing another portion of the split gate pattern by an anisotropic etching process or a wet etching process; and removing the photoresist pattern.
References Cited (Backward Citations)
US4925807A
Cited
JPH0223672A
Cited
US5041886A
Cited
US5268585A
Cited
US5364806A
Cited
US5455792A
Cited
US5607871A
Cited
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| 3.5 Years (Year 4) | 2002-04-05 | 2002-10-05 | 2003-04-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-04-05 | 2006-10-05 | 2007-04-06 | $3760.00 | Window Closed / Lapsed |
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