Semiconductor memory device

Abstract

Abstract PURPOSE:To keep unchanged a capacitive coupling ratio between a control gate and a floating gate by reducing a cell area and defining channel length in a self-alignment manner by forming the control gate on the source side wall of the floating gate in a self-alignment manner. CONSTITUTION:After a floating gate 2 is formed, a control gate 3 is formed on the gate 2 and on a source 4 side wall of the gate 2. Thereupon, the gate 3 on the side wall is formed in a self-alignment manner. By forming the control gate in a self-alignment manner the control gate forms a channel between it and a substrate only on the source side wall. Accordingly, channel length of a memory transistor is decided substantially by floating gate length to result in a reduced cell area. Additionally, almost all of capacitive coupling ratio between the floating gate and the control gate is decided by a lamination portion between the control gate on the floating gate and the floating gate. Therefore, there are produced no variations of the capacitive coupling ratio due to misalignment upon pattern formation.

Inventors

• 👤 Hideaki Arima
• 👤 有馬　秀明
• 👤 Natsuo Ajika
• 👤 夏夫 味香
• 👤 Shinichi Sato
• 👤 真一 佐藤
• 👤 Giyoto Watabe
• 👤 毅代登 渡部

Bibliographic Details