US5890201A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Content addressable memory having memory cells storing don't care states for address translation
Assignee: Hewlett Packard Development Co LP
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Filing: 1997-07-01
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Granted: 1999-03-30
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Expires: 2017-07-01
Abstract
Abstract A method of accessing a content addressable memory storing two bits of information representing either an invalid state, a logic zero state, a logic one state, or a don't care state, is disclosed. The stored information is compared with a one bit signal. A match is indicated when the one bit signal represents a logic zero and the stored information represents the don't care state, or when the one bit signal represents a logic one and the stored information represents a don't care state. An absence of a match is indicated when the one bit signal represents a logic zero and the stored information represents an invalid state, or when the one bit signal represents a logic one and the stored information represents the invalid state. The content addressable memory is especially adapted for use in a translation buffer providing variable page granularity. The don't care state permits multiple virtual page numbers to match a single entry storing information for multiple physical pages. The invalid state eliminates the need for a dedicated valid bit in each entry.
Inventors
- 👤 Edward J. McLellan
- 👤 Bruce A. Gieseke
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 16:59
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/10; G06F12/1027; G11; G11C; G11C15/00; G11C15/04; G06F2212/00; G06F2212/65; G06F2212/652
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
422 words
A method of accessing a memory with a one-bit signal, said memory having a pair of single-bit storage locations together storing two bits of information representing either an invalid state, a logic zero state, a logic one state, or a don't care state; said method comprising the steps of: a) storing information in said pair of storage locations representing said invalid state, generating a signal indicating an absence of a match when said one-bit signal represents a logic zero and the information stored in said pair of storage locations represents said invalid state, and generating a signal indicating an absence of a match when said one-bit signal represents a logic one and the information stored in said pair of storage locations represents said invalid state; b) storing information in said pair of storage locations representing said logic zero state, generating a signal indicating a presence of a match when said one-bit signal represents a logic zero and the information stored in said pair of storage locations represents said logic zero state, and generating a signal indicating an absence of a match when said one-bit signal represents a logic one and the information stored in said pair of storage locations represents said logic zero state; c) storing information in said pair of storage locations representing said logic one state, and generating a signal indicating an absence of a match when said one-bit signal represents a logic zero and the information stored in said pair of storage locations represents said logic one state, and generating a signal indicating a presence of a match when said one-bit signal represents a logic one and the information stored in said pair of storage locations represents and said logic one state; d) storing information in said pair of storage locations representing said don't care state, generating a signal indicating a presence of a match when said one-bit signal represents a logic zero and the information stored in said pair of storage locations represents said don't care state, and generating a signal indicating a presence of a match when said one-bit signal represents a logic one and the information stored in said pair of storage locations represents said don't care state; and wherein said step of storing information in said pair of storage locations representing said invalid state includes a step of asserting a flush signal on a flush line, said flush line coupled with each of said pair of storage locations, said flush signal causing each of said pair of storage locations to equal a predetermined logical value.
Claim 2
Independent Claim
422 words
A method of accessing a memory with a one-bit signal, said memory having a pair of single-bit storage locations together storing two bits of information representing either an invalid state, a logic zero state, a logic one state, or a don't care state; said method comprising the steps of: a) storing information in said pair of storage locations representing said invalid state, generating a signal indicating an absence of a match when said one-bit signal represents a logic zero and the information stored in said pair of storage locations represents said invalid state, and generating a signal indicating an absence of a match when said one-bit signal represents a logic one and the information stored in said pair of storage locations represents said invalid state; b) storing information in said pair of storage locations representing said logic zero state, generating a signal indicating a presence of a match when said one-bit signal represents a logic zero and the information stored in said pair of storage locations represents said logic zero state, and generating a signal indicating an absence of a match when said one-bit signal represents a logic one and the information stored in said pair of storage locations represents said logic zero state; c) storing information in said pair of storage locations representing said logic one state, and generating a signal indicating an absence of a match when said one-bit signal represents a logic zero and the information stored in said pair of storage locations represents said logic one state, and generating a signal indicating a presence of a match when said one-bit signal represents a logic one and the information stored in said pair of storage locations represents and said logic one state; d) storing information in said pair of storage locations representing said don't care state, generating a signal indicating a presence of a match when said one-bit signal represents a logic zero and the information stored in said pair of storage locations represents said don't care state, and generating a signal indicating a presence of a match when said one-bit signal represents a logic one and the information stored in said pair of storage locations represents said don't care state; and wherein said step of storing information in said pair of storage locations representing said invalid state includes a step of asserting a flush signal on a flush line, said flush line coupled with each of said pair of storage locations, said flush signal causing each of said pair of storage locations to equal a predetermined logical value.
Claim 3
Dependent Claim
43 words
The method as claimed in claim 1, further comprising the steps of precharging a match line on which the signals indicating a presence of a match are generated, and discharging the match line whenever generating a signal indicating an absence of a match.
Claim 4
Dependent Claim
63 words
The method as claimed in claim 1, which includes the steps of complementing said one-bit signal to produce a complemented bit signal, comparing said one-bit signal to a single bit of information stored in one of said pair of storage locations, and comparing said complemented bit signal to a single bit of information stored in another one of said pair of storage locations.
Claim 5
Dependent Claim
52 words
The method as claimed in claim 1, wherein said step of storing information in said pair of storage locations representing said don't care state includes a step of masking an input data bit with a mask bit to produce a result that is stored in one of said pair of storage locations.
References Cited (Backward Citations)
US3717848A
Cited
US3675215A
Cited
US3761902A
Cited
US3806890A
Cited
US4638426A
Cited
US4602368A
Cited
US4538241A
Cited
US4831585A
Cited
US4879687A
Cited
US4813002A
Cited
US4799192A
Cited
US5014327A
Cited
US5051949A
Cited
US5491806A
Cited
US5193167A
Cited
US5155843A
Cited
US5454091A
Cited
US5222222A
Cited
US5263140A
Cited
EP0496288A2
Cited
US5351208A
Cited
US5450558A
Cited
US5319590A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-03-29 | 2002-09-28 | 2003-03-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-03-29 | 2006-09-28 | 2007-03-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-03-29 | 2010-09-28 | 2011-03-30 | $7700.00 | Window Closed / Lapsed |