US5890191A — Method and apparatus for providing erasing and pr…

Claim 1

Independent Claim 226 words

A method for operating an Electrically Erasable PROM array, comprising steps of: receiving a request to erase or program the Electrically Erasable PROM array, wherein said step of receiving a request comprises a step of receiving a plurality of address signals; and requiring a sequence of steps to selectively enable erasing or programming of the Electrically Erasable PROM array; the sequence of steps to selectively enable erasing or programming of the Electrically Erasable PROM array comprising steps of: performing a software read access to a block protect register, the block protect register storing a block protect value; comparing at least a portion of the block protect value to at least a portion of the plurality of address signals; if the at least a portion of the block protect value corresponds to the at least a portion of the plurality of address signals, inhibiting erasing and programming of the Electrically Erasable PROM array; if the at least a portion of the block protect value does not corresponds to the at least a portion of the plurality of address signals, continuing the sequence of steps to selectively enable erasing or programming of the Electrically Erasable PROM array; performing a write access to a charge pump enable bit to assert the charge pump enable bit; and if the charge pump enable bit is successfully asserted, enabling a charge pump.

Claim 2

Independent Claim 226 words

A method for operating an Electrically Erasable PROM array, comprising steps of: receiving a request to erase or program the Electrically Erasable PROM array, wherein said step of receiving a request comprises a step of receiving a plurality of address signals; and requiring a sequence of steps to selectively enable erasing or programming of the Electrically Erasable PROM array; the sequence of steps to selectively enable erasing or programming of the Electrically Erasable PROM array comprising steps of: performing a software read access to a block protect register, the block protect register storing a block protect value; comparing at least a portion of the block protect value to at least a portion of the plurality of address signals; if the at least a portion of the block protect value corresponds to the at least a portion of the plurality of address signals, inhibiting erasing and programming of the Electrically Erasable PROM array; if the at least a portion of the block protect value does not corresponds to the at least a portion of the plurality of address signals, continuing the sequence of steps to selectively enable erasing or programming of the Electrically Erasable PROM array; performing a write access to a charge pump enable bit to assert the charge pump enable bit; and if the charge pump enable bit is successfully asserted, enabling a charge pump.

Claim 3

Dependent Claim 19 words

A method as in claim 1, wherein the block protect register is located within the Electrically Erasable PROM array.

Claim 4

Dependent Claim 21 words

A method as in claim 2, wherein the charge pump enable bit is not located within the Electrically Erasable PROM array.

Claim 5

Dependent Claim 48 words

A method as in claim 1, herein said step of inhibiting erasing and programming of the Electrically Erasable PROM array comprises a step of determining that the at least a portion of the block protect value matches the at least a portion of the plurality of address signals.

Claim 6

Dependent Claim 198 words

An integrated circuit, comprising: an Electrically Erasable PROM memory array; a charge pump circuit, coupled to said Electrically Erasable PROM memory array, said charge pump circuit providing a voltage to said Electrically Erasable PROM memory array for erasing and programming said Electrically Erasable PROM memory array; protection sequence circuitry for requiring that a sequence of steps be performed to enable erasing and programming of said Electrically Erasable PROM memory array; charge pump protection circuitry, coupled to said charge pump and to said protection sequence circuitry, said charge pump protection circuitry enabling operation of said charge pump circuit as a result of said protection sequence circuitry indicating that the sequence of steps to enable erasing and programming of said Electrically Erasable PROM memory array had been successfully completed; and a processor, coupled to said Electrically Erasable PROM memory array, said processor executing a plurality of instructions as part of the sequence of steps to enable erasing and programming of said Electrically Erasable PROM memory array; wherein said plurality of instructions includes a first instruction which performs a read access as part of the sequence of steps performed to enable erasing and programming of said Electrically Erasable PROM memory array.

Claim 7

Dependent Claim 198 words

An integrated circuit, comprising: an Electrically Erasable PROM memory array; a charge pump circuit, coupled to said Electrically Erasable PROM memory array, said charge pump circuit providing a voltage to said Electrically Erasable PROM memory array for erasing and programming said Electrically Erasable PROM memory array; protection sequence circuitry for requiring that a sequence of steps be performed to enable erasing and programming of said Electrically Erasable PROM memory array; charge pump protection circuitry, coupled to said charge pump and to said protection sequence circuitry, said charge pump protection circuitry enabling operation of said charge pump circuit as a result of said protection sequence circuitry indicating that the sequence of steps to enable erasing and programming of said Electrically Erasable PROM memory array had been successfully completed; and a processor, coupled to said Electrically Erasable PROM memory array, said processor executing a plurality of instructions as part of the sequence of steps to enable erasing and programming of said Electrically Erasable PROM memory array; wherein said plurality of instructions includes a first instruction which performs a read access as part of the sequence of steps performed to enable erasing and programming of said Electrically Erasable PROM memory array.

Claim 8

Dependent Claim 19 words

An integrated circuit as in claim 5, further comprising: a first storage circuit for storing a block protect value.

Claim 9

Dependent Claim 36 words

An integrated circuit, as in claim 6, further comprising: a signal, received from external to the integrated circuit, the signal being required to erase or program the first storage circuit which stores the block protect value.

Claim 10

Dependent Claim 26 words

An integrated circuit as in claim 6, where said first storage circuit storing the block protect value is located within said Electrically Erasable PROM memory array.

Claim 11

Dependent Claim 20 words

An integrated circuit as in claim 6, further comprising: a second storage circuit for storing a charge pump enable value.

Claim 12

Dependent Claim 28 words

An integrated circuit as in claim 9, where said second storage circuit storing the charge pump enable value is not located within said Electrically Erasable PROM memory array.

Claim 13

Dependent Claim 14 words

An integrated circuit as in claim 5, wherein said integrated circuit comprises a microcontroller.

Claim 14

Dependent Claim 20 words

An integrated circuit, as in claim 5, wherein said read access accesses a register that stores a block protect value.

Claim 15

Dependent Claim 41 words

An integrated circuit, as in claim 5, wherein said plurality of instructions includes a second instruction which performs a write access as part of the sequence of steps performed to enable erasing and programming of said Electrically Erasable PROM memory array.

Claim 16

Dependent Claim 68 words

An integrated circuit, as in claim 13, further comprising: a first storage circuit for storing a block protect value; and a second storage circuit for storing a charge pump enable value; wherein the read access by said processor is to the first storage circuit for reading the block protect value, and wherein the write access is to the second storage circuit for writing the charge pump enable value.

Claim 17

Dependent Claim 171 words

A block erasable Electrically Erasable PROM memory apparatus for use in a microcontroller, comprising: a memory array of Electrically Erasable PROM (EEPROM) memory cells having a programming voltage terminal for receiving a programming voltage to allow writing of data to the EEPROM; a charge pump having a charge pump enable input for receiving an enable signal, wherein the charge pump is used for generating the programming voltage, when the enable signal is active; and a protect control block coupled to the charge pump for generating an active enable signal when a memory area of the memory array is in a write state, and generating an inactive enable signal when the memory area is in a protected state; wherein the protect control block comprises: a write protect memory area for identifying which portions of the memory array are in a protected state; and a decode block coupled to the write protect memory area, wherein the decode block generates the enable signal based on a value stored in the write protect memory area.

Claim 18

Dependent Claim 171 words

A block erasable Electrically Erasable PROM memory apparatus for use in a microcontroller, comprising: a memory array of Electrically Erasable PROM (EEPROM) memory cells having a programming voltage terminal for receiving a programming voltage to allow writing of data to the EEPROM; a charge pump having a charge pump enable input for receiving an enable signal, wherein the charge pump is used for generating the programming voltage, when the enable signal is active; and a protect control block coupled to the charge pump for generating an active enable signal when a memory area of the memory array is in a write state, and generating an inactive enable signal when the memory area is in a protected state; wherein the protect control block comprises: a write protect memory area for identifying which portions of the memory array are in a protected state; and a decode block coupled to the write protect memory area, wherein the decode block generates the enable signal based on a value stored in the write protect memory area.

Claim 19

Dependent Claim 17 words

The apparatus of claim 15, wherein the protect control block further comprises: a charge pump enable bit.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2002-03-29	2002-09-28	2003-03-30	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2006-03-29	2006-09-28	2007-03-30	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2010-03-29	2010-09-28	2011-03-30	$7700.00	Window Closed / Lapsed

Method and apparatus for providing erasing and programming protection for electrically erasable programmable read only memory

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