US5890189A — Memory management and protection system for virtu…

Claim 1

Independent Claim 179 words

A memory management and protection system for controlling memory accesses to a logical address space managed in terms of segments, comprising: segment information extraction means for obtaining a target segment identifier for identifying a target segment containing a logical address to be accessed in the segments of the logical address space, according to the logical address; memory protection information extraction means for obtaining a target memory protection information for a target region containing the logical address to be accessed in the target segment identified by the target segment identifier, according to the logical address, the memory protection information including a target right permission to indicate assigned rights to make a memory access from the target region to each of the segments of the logical address space, and a target execution permission to indicate a type of the memory access permitted by the target right permission as one of instruction access and data access; and memory access permission means for permitting the memory access to the logical address according to the target segment identifier and the target memory protection information.

Claim 2

Dependent Claim 179 words

A memory management and protection system for controlling memory accesses to a logical address space managed in terms of segments, comprising: segment information extraction means for obtaining a target segment identifier for identifying a target segment containing a logical address to be accessed in the segments of the logical address space, according to the logical address; memory protection information extraction means for obtaining a target memory protection information for a target region containing the logical address to be accessed in the target segment identified by the target segment identifier, according to the logical address, the memory protection information including a target right permission to indicate assigned rights to make a memory access from the target region to each of the segments of the logical address space, and a target execution permission to indicate a type of the memory access permitted by the target right permission as one of instruction access and data access; and memory access permission means for permitting the memory access to the logical address according to the target segment identifier and the target memory protection information.

Claim 3

Dependent Claim 135 words

The system of claim 1, further comprising: current segment identifier storage means for storing a current segment identifier for identifying a current segment in which a currently executed instruction is present in the segments of the logical address space; and current memory protection information storage means for storing a current memory protection information for a current region in which the currently executed instruction is present in the current segment identified by the current segment identifier, the current memory protection information including a current right permission to indicate assigned rights to make a memory access from the current region to each of the segments of the logical address space, and a current execution permission to indicate a type of the memory access permitted by the current right permission as one of instruction access and data access.

Claim 4

Dependent Claim 59 words

The system of claim 2, wherein the memory access permission means permits the instruction access according to the current memory protection information, the target memory protection information, and the target segment identifier, while the memory access permission means permits the data access according to the target segment identifier and the target memory protection information, and the current segment identifier.

Claim 5

Dependent Claim 57 words

The system of claim 2, wherein the target memory protection information further includes a target transition permission to indicate the target region as a gate region accessible from all the segments in the logical address space, and the current memory protection information further includes a current transition permission to indicate the current region as the gate region.

Claim 6

Dependent Claim 142 words

The system of claim 4, wherein the memory access permission means permits the instruction access in the following three cases: (1) the current right permission asserts the assigned right to make the memory access from the current region to the target segment identified by the target segment identifier, and the target execution permission asserts the type of the memory access permitted by the target right permission as the instruction access; (2) the current execution permission asserts the type of the memory access permitted by the current right permission as the instruction access, and the target transition permission asserts the target region as the gate region; and (3) the current transition permission asserts the current region as the gate region, and the target execution permission asserts the type of the memory access to be made to the logical address as the instruction access.

Claim 7

Dependent Claim 43 words

The system of claim 2, wherein the memory access permission means permits the data access when the target right permission asserts the assigned right to make the memory access from the target region to the current segment identified by the current segment identifier.

Claim 8

Dependent Claim 73 words

The system of claim 6, wherein the target memory protection information further includes a read permission to indicate the logical address to be accessed as readable, and a write permission to indicate the logical address to be accessed as writable, such that the memory access permission means permits the data access for data read when the read permission is asserted and the data access for data write when the write permission is asserted.

Claim 9

Dependent Claim 73 words

The system of claim 2, further comprising means for updating the current segment identifier stored in the current segment identifier storage means by the target segment identifier obtained by the segment information extraction means, and the current memory protection information stored in the current memory protection information storage means by the target memory protection information obtained by the memory protection information extraction means, whenever the memory access permission means permits the instruction access.

Claim 10

Dependent Claim 44 words

The system of claim 1, further comprising means for generating a segment transition notice when the target segment identified by the target segment identifier and the current segment identified by the current segment identifier are not identical in a case of the instruction access.

Claim 11

Dependent Claim 26 words

The system of claim 1, wherein the segment information extraction means obtains the target segment identifier as upper bits of the logical address to be accessed.

Claim 12

Dependent Claim 150 words

A memory management system for converting a logical address into a physical address in a computer which executes a plurality of programs allocated to a virtual space in parallel by activating a plurality of threads, comprising: access permission memory means for storing access permissions indicating whether each thread is permitted to make accesses to the logical address; a thread number memory for storing a thread number assigned to a currently executing thread which is currently executing the programs; verification means for verifying whether the currently executing thread specified by the thread number stored in the thread number memory is permitted to make accesses to the logical address, according to the access permissions stored in the access permission memory means; and means for outputting the physical address converted from the logical address when the verification means verifies that the currently executing thread is permitted to make accesses to the logical address.

Claim 13

Dependent Claim 150 words

A memory management system for converting a logical address into a physical address in a computer which executes a plurality of programs allocated to a virtual space in parallel by activating a plurality of threads, comprising: access permission memory means for storing access permissions indicating whether each thread is permitted to make accesses to the logical address; a thread number memory for storing a thread number assigned to a currently executing thread which is currently executing the programs; verification means for verifying whether the currently executing thread specified by the thread number stored in the thread number memory is permitted to make accesses to the logical address, according to the access permissions stored in the access permission memory means; and means for outputting the physical address converted from the logical address when the verification means verifies that the currently executing thread is permitted to make accesses to the logical address.

Claim 14

Dependent Claim 76 words

The system of claim 11, wherein the access permissions stored in the access permission memory means indicate thread numbers assigned to those threads which are permitted to make accesses, and the verification means verifies that the currently executing thread is permitted to make accesses to the logical address when a matching of the thread number specified by the thread number memory with one of the thread numbers indicated by the access permission memory means is found.

Claim 15

Dependent Claim 70 words

The system of claim 12, wherein the verification means checks the matching of the thread number specified by the thread number memory with each one of the thread numbers indicated by the access permission memory means by masking at least a part of either one of the thread number specified by the thread number memory or said each one of the thread numbers indicated by the access permission memory means.

Claim 16

Dependent Claim 41 words

The system of claim 13, wherein the masking masks a whole of either one of the thread number specified by the thread number memory or said each one of the thread numbers indicated by the access permission memory means at most.

Claim 17

Dependent Claim 64 words

The system of claim 11, wherein the verification means verifies that the currently executing thread is permitted to make accesses to the logical address when a prescribed logical calculation for the thread number specified by the thread number memory and one of the thread numbers indicated by the access permission memory means comes up with a result indicating the prescribed logical calculation as true.

Claim 18

Dependent Claim 147 words

A memory management system for converting a logical address into a physical address in a computer which executes programs allocated to a virtual space divided into a plurality of address regions, comprising: access permission memory means for storing access permissions indicating whether accesses from each program allocated to each address region to the logical address are permitted; address region detection deans for detecting a current address region containing a currently executing program which makes an access to the logical address; verification means for verifying whether accesses from the current address region detected by the address region detection means to the logical address are permitted, according to the access permissions stored in the access permission memory means; and means for outputting the physical address converted from the logical address when the verification means verifies that the accesses from the current address region to the logical address are permitted.

Claim 19

Dependent Claim 147 words

A memory management system for converting a logical address into a physical address in a computer which executes programs allocated to a virtual space divided into a plurality of address regions, comprising: access permission memory means for storing access permissions indicating whether accesses from each program allocated to each address region to the logical address are permitted; address region detection deans for detecting a current address region containing a currently executing program which makes an access to the logical address; verification means for verifying whether accesses from the current address region detected by the address region detection means to the logical address are permitted, according to the access permissions stored in the access permission memory means; and means for outputting the physical address converted from the logical address when the verification means verifies that the accesses from the current address region to the logical address are permitted.

Claim 20

Dependent Claim 86 words

The system of claim 16, wherein the access permissions stored in the access permission memory means indicate address region numbers assigned to those address regions from which accesses are permitted, and the verification means verifies that the accesses from the current address region to the logical address are permitted, when a matching of an address region number assigned to the current address region detected by the address region detection means with one of the address region numbers indicated by the access permission memory means is found.

Claim 21

Dependent Claim 88 words

The system of claim 17, wherein the verification means checks the matching of the address region number assigned to the current address region detected by the address region detection means with each one of the address region numbers indicated by the access permission memory means by masking at least a part of either one of the address region number assigned to the current address region detected by the address region detection means or said each one of the address region numbers indicated by the access permission memory means.

Claim 22

Dependent Claim 50 words

The system of claim 18, wherein the masking masks a whole of either one of the address region number assigned to the current address region detected by the address region detection means or said each one of the address region numbers indicated by the access permission memory means at most.

Claim 23

Dependent Claim 73 words

The system of claim 16, wherein the verification means verifies that the accesses from the current address region to the logical address are permitted, when a prescribed logical calculation for the address region number assigned to the current address region detected by the address region detection means and one of the address region numbers indicated by the access permission memory means comes up with a result indicating the prescribed logical calculation as true.

Claim 24

Dependent Claim 103 words

A memory management system for converting a logical address into a physical address, comprising: access permission memory means for storing access permissions for accesses from each program allocated to a logical address space with respect to the logical address; verification means for verifying whether accesses from a currently executing program with respect to the logical address are permitted, according to the access permissions stored in the access permission memory means; and means for outputting the physical address converted from the logical address when the verification means verifies that the accesses from the currently executing program with respect to the logical address are permitted.

Claim 25

Dependent Claim 103 words

A memory management system for converting a logical address into a physical address, comprising: access permission memory means for storing access permissions for accesses from each program allocated to a logical address space with respect to the logical address; verification means for verifying whether accesses from a currently executing program with respect to the logical address are permitted, according to the access permissions stored in the access permission memory means; and means for outputting the physical address converted from the logical address when the verification means verifies that the accesses from the currently executing program with respect to the logical address are permitted.

Claim 26

Dependent Claim 34 words

The system of claim 21, wherein the access permissions indicate whether the accesses to the logical address from a position in the logical address space at which said each program is located are permitted.

Claim 27

Dependent Claim 28 words

The system of claim 21, wherein the access permissions indicate whether the accesses to the logical address from a thread which is executing said each program are permitted.

Claim 28

Dependent Claim 142 words

The system of claim 21, further comprising: a cache memory for storing a predetermined number of cached address table entries; a cache access permission memory for storing a fixed number of access permissions for accesses from each program allocated to the logical address space with respect to each logical address stored in each cached address table entry of the cache memory; cache verification means for verifying whether accessed from a currently executing program with respect to one logical address stored in one cached address table entry of the cache memory are permitted, according to the access permissions stored in the cache access permission memory; and means for outputting a physical address stored in said one cached address table entry, when the cache verification means verifies that the accesses from the currently executing program with respect to said one logical address are permitted.

Claim 29

Dependent Claim 76 words

The system of claim 24, further comprising: means for replacing the fixed number of access permissions for accesses from said each program by at most the fixed number of additional access permissions different from said fixed number of access permissions for accesses from said each program, when the cache verification means fails to verify said fixed number of access permissions for accesses from the currently executing program with respect to the logical address to be accessed.

Claim 30

Dependent Claim 178 words

A memory management and protection system, comprising: program allocation means for determining an allocation of a plurality of programs to at least one of logical address spaces, where only up to a predetermined number of the programs are allocated to each logical address space, and any one address region allocated to any one of the programs does not overlap with any other address regions allocated to any other ones of the programs within said at least one of the logical address spaces; memory protection means for detecting an occurrence of an improper access from one address region allocated to one of the programs to another address region allocated to another one of the programs, among said up to the predetermined number of the programs allocated to said each logical address space; cache means for storing data to be accessed by the programs; and processing means for executing the programs by making accesses to the cache means according to the allocation determined by the program allocation means, unless the memory protection means detects the occurrence of the improper access.

Claim 31

Dependent Claim 178 words

A memory management and protection system, comprising: program allocation means for determining an allocation of a plurality of programs to at least one of logical address spaces, where only up to a predetermined number of the programs are allocated to each logical address space, and any one address region allocated to any one of the programs does not overlap with any other address regions allocated to any other ones of the programs within said at least one of the logical address spaces; memory protection means for detecting an occurrence of an improper access from one address region allocated to one of the programs to another address region allocated to another one of the programs, among said up to the predetermined number of the programs allocated to said each logical address space; cache means for storing data to be accessed by the programs; and processing means for executing the programs by making accesses to the cache means according to the allocation determined by the program allocation means, unless the memory protection means detects the occurrence of the improper access.

Claim 32

Dependent Claim 151 words

The system of claim 26, further comprising: logical address space switching detection means for detecting an occurrence of a logical address space switching from one of the logical address spaces to another one of the logical address spaces, in conjunction with a context switching of a program to be executed from a switch requesting program to a switch target program among the plurality of programs; and cache validation/invalidation means for invalidating those data stored in the cache means which belong to the switch requesting program when the logical address space switching detection means detects the occurrence of the logical address space switching; wherein the processing means executes each one of the programs by making accesses to the cache means unless the memory protection means detects the occurrence of the improper access and the data to be accessed by said each one of the programs are invalidated by the cache validation/invalidation means.

Claim 33

Dependent Claim 66 words

The system of claim 27, wherein the program allocation means determines the allocation of the plurality of programs to said at least one of the logical address spaces, according to a program management table indicating a utilization state of each address region in the logical address spaces along with a logical address space number of each logical address space to which said each address region belongs.

Claim 34

Dependent Claim 69 words

The system of claim 28, wherein the logical address space switching detection means detects the occurrence of the logical address space switching by comparing the logical address space number for a switch requesting address region to which the switch requesting program is allocated and the logical address space number for a switch target address region to which the switch target program is allocated, according to the program management table.

Claim 35

Dependent Claim 43 words

The system of claim 27, wherein the cache validation/invalidation means also validates those data stored in the cache means which belong to the switch target program when the logical address space switching detection means detects the occurrence of the logical address space switching.

Claim 36

Dependent Claim 82 words

The system of claim 27, wherein the cache validation/invalidation means also invalidates those data stored in the cache means which belong to said one of the logical address spaces to which the switch requesting program is allocated and validates those data stored in the cache means which belong to said another one of the logical address spaces to which the switch target program is allocated, when the logical address space switching detection means detects the occurrence of the logical address space switching.

Claim 37

Dependent Claim 187 words

The system of claim 26, further comprising logical address space switching detection means for detecting an occurrence of a logical address space switching from one of the logical address spaces to another one of the logical address spaces, in conjunction with a context switching of a program to be executed from a switch requesting program to a switch target program among the plurality of programs; and a translation look-aside buffer (TLB) means having a plurality of TLB entries, each TLB entry storing a logical address of the data to be accessed stored in the cache means, a physical address corresponding to the logical address, and an invalidation bit for indicating a validity of said each TLB entry; wherein the processing means makes accesses to the cache means for data to be accessed by said each one of the programs, while checking the TLB means to determine whether the data to be accessed by said each one of the programs is accessible according to the invalidation bit of the TLB entry storing the logical address of the data to be accessed by said each one of the programs.

Claim 38

Dependent Claim 69 words

The system of claim 26, wherein the program allocation means allocates the plurality of programs to said at least one of logical address spaces according to frequencies of occurrences of accesses between each two programs among the plurality of programs, such that closely related programs for which the frequencies of occurrences of accesses are higher are allocated to an identical one of the logical address spaces at higher priority.

Claim 39

Dependent Claim 101 words

The system of claim 33, wherein when a number of the closely related programs exceeds the predetermined number, the program allocation means allocates the predetermined number of the closely related programs to the identical one of the logical address spaces, while allocating each remaining one of the closely related programs in excess of the predetermined number to an additional logical address space provided in addition to said at least one of the logical address spaces, along with a duplicate of a part of the predetermined number of the closely related programs allocated to the identical one of the logical address spaces.

Claim 40

Dependent Claim 61 words

The system of claim 26, wherein the program allocation means allocates the plurality of programs to said at least one of logical address spaces such that at most one execution program, which is capable of executing an instruction for any one of reading from another program, writing to another program, and executing another program, is allocated to each logical address space.

Claim 41

Dependent Claim 34 words

The system of claim 35, further comprising access mode assignment means for indicating access modes permitted to each one of the plurality of programs with respect to other ones of the plurality of programs.

Claim 42

Dependent Claim 32 words

The system of claim 35, wherein the program allocation means allocates each execution program to said each logical address space along with other programs which are accessible from said each execution program.

Claim 43

Dependent Claim 148 words

The system of claim 26, wherein the program allocation means allocates the plurality of programs to said at least one of logical address spaces such that at most one unique access mode assigned execution program, which is capable of executing an instruction for any one of reading from another program, writing to another program, and executing another program, and which has unique access modes with respect to other ones of the plurality of programs, can be allocated to each logical address space, while any number of non-unique access mode assigned execution programs, each of which is capable of executing an instruction for any one of reading from another program, writing to another program, and executing another program, and each of which has identical access modes with respect to other ones of the plurality of programs as another non-unique execution program, can be allocated to each logical address space.

Claim 44

Independent Claim 141 words

A method of memory management for converting a logical address into a physical address in a computer which executes a plurality of programs allocated to a virtual space in parallel by activating a plurality of threads, the method comprising the steps of: storing, in an access permission memory means, access permissions indicating whether each thread is permitted to make accesses to the logical address; storing a thread number assigned to a currently executing thread which is currently executing the programs; verifying whether the currently executing thread specified by the thread number is permitted to make accesses to the logical address, according to the access permissions stored in the access permission memory means; and outputting the physical address converted from the logical address when the verifying step verifies that the currently executing thread is permitted to make accesses to the logical address.

Claim 45

Independent Claim 141 words

A method of memory management for converting a logical address into a physical address in a computer which executes a plurality of programs allocated to a virtual space in parallel by activating a plurality of threads, the method comprising the steps of: storing, in an access permission memory means, access permissions indicating whether each thread is permitted to make accesses to the logical address; storing a thread number assigned to a currently executing thread which is currently executing the programs; verifying whether the currently executing thread specified by the thread number is permitted to make accesses to the logical address, according to the access permissions stored in the access permission memory means; and outputting the physical address converted from the logical address when the verifying step verifies that the currently executing thread is permitted to make accesses to the logical address.

Claim 46

Independent Claim 143 words

A method of memory management for converting a logical address into a physical address in a computer which executes programs allocated to a virtual space divided into a plurality of address regions, the method comprising the steps of: storing, in an access permission memory means, access permissions indicating whether accesses from each program allocated to each address region to the logical address are permitted; detecting a current address region containing a currently executing program which makes an access to the logical address; verifying whether the accesses from the current address region detected at the detecting step to the logical address are permitted, according to the access permissions stored in the access permission memory means; and outputting the physical address converted from the logical address when the verifying step verifies that the accesses from the current address region to the logical address are permitted.

Claim 47

Independent Claim 143 words

A method of memory management for converting a logical address into a physical address in a computer which executes programs allocated to a virtual space divided into a plurality of address regions, the method comprising the steps of: storing, in an access permission memory means, access permissions indicating whether accesses from each program allocated to each address region to the logical address are permitted; detecting a current address region containing a currently executing program which makes an access to the logical address; verifying whether the accesses from the current address region detected at the detecting step to the logical address are permitted, according to the access permissions stored in the access permission memory means; and outputting the physical address converted from the logical address when the verifying step verifies that the accesses from the current address region to the logical address are permitted.

Claim 48

Independent Claim 103 words

A method of memory management for converting a logical address into a physical address, comprising the steps of: storing, in an access permission memory means, access permissions for accesses from each program allocated to a logical address space with respect to the logical address; verifying whether accesses from a currently executing program with respect to the logical address are permitted, according to the access permissions stored in the access permission memory means; and outputting the physical address converted from the logical address when the verifying step verifies that the accesses from the currently executed program with respect to the logical address are permitted.

Claim 49

Independent Claim 103 words

A method of memory management for converting a logical address into a physical address, comprising the steps of: storing, in an access permission memory means, access permissions for accesses from each program allocated to a logical address space with respect to the logical address; verifying whether accesses from a currently executing program with respect to the logical address are permitted, according to the access permissions stored in the access permission memory means; and outputting the physical address converted from the logical address when the verifying step verifies that the accesses from the currently executed program with respect to the logical address are permitted.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2002-03-29	2002-09-28	2003-03-30	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2006-03-29	2006-09-28	2007-03-30	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2010-03-29	2010-09-28	2011-03-30	$7700.00	Window Closed / Lapsed

Memory management and protection system for virtual memory in computer system

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