US5481689A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Conversion of internal processor register commands to I/O space addresses
Assignee: Hewlett Packard Development Co LP
•
Filing: 1993-08-13
•
Granted: 1996-01-02
•
Expires: 2013-08-13
Abstract
Abstract A pipelined CPU executing instructions of variable length, and referencing memory using various data widths. Macroinstruction pipelining is employed (instead of microinstruction pipelining), with queuing between units of the CPU to allow flexibility in instruction execution times. A wide bandwidth is available for memory access; fetching 64-bit data blocks on each cycle. Internal processor registers are accessed with short (byte width) addresses instead of full physical addresses as used for memory and I/O references, but off-chip processor registers are memory-mapped and accessed by the same busses using the same controls as the memory and I/O.
Inventors
- 👤 Rebecca L. Stamm
- 👤 G. Michael Uhler
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 07:43
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3836; G06F9/30003; G06F9/30007; G06F9/30036; G06F9/30038; G06F9/30098; G06F9/3012; G06F9/30134; G06F9/30138; G06F9/30145; G06F9/3016; G06F9/30167; G06F9/3802; G06F9/3804; G06F9/3806; G06F9/3838; G06F9/3854; G06F9/3856; G06F9/3858; F; F02; F02B; F02B75/00; F02B75/02; F02B2075/022; F02B2075/025; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1064; G06F11/22
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
207 words
A method of addressing a plurality of processor registers in a computer system including a processor device, said processor device being in communication with said plurality of processor registers, said plurality of processor registers including processor registers within said processor device and also including processor registers external to said processor device, comprising the steps of: a) generating within said processor device a short address defining a range of addresses including addresses of all of said plurality of processor registers, said short address including a number of bits, wherein said processor registers external to said processor device are mapped in a given address space of said computer system, said given address space being a main memory space of said computer system; b) accessing one of said processor registers within said processor device using said short address if said short address identifies a processor register within said processor device; and c) accessing one of said processor registers external to said processor device using an external address longer than said short address and consisting of said short address without translation plus at least one high order address bit, if said short address identifies a processor register external to said processor device, said external address being within said given address space.
Claim 2
Independent Claim
207 words
A method of addressing a plurality of processor registers in a computer system including a processor device, said processor device being in communication with said plurality of processor registers, said plurality of processor registers including processor registers within said processor device and also including processor registers external to said processor device, comprising the steps of: a) generating within said processor device a short address defining a range of addresses including addresses of all of said plurality of processor registers, said short address including a number of bits, wherein said processor registers external to said processor device are mapped in a given address space of said computer system, said given address space being a main memory space of said computer system; b) accessing one of said processor registers within said processor device using said short address if said short address identifies a processor register within said processor device; and c) accessing one of said processor registers external to said processor device using an external address longer than said short address and consisting of said short address without translation plus at least one high order address bit, if said short address identifies a processor register external to said processor device, said external address being within said given address space.
Claim 3
Dependent Claim
16 words
A method according to claim 1 wherein said short address is no wider than a byte.
Claim 4
Dependent Claim
41 words
A method according to claim 2 wherein said at least one high order address bit is a plurality of bits, and wherein an address for said processor register external to said processor device is an address of at least four bytes.
Claim 5
Dependent Claim
21 words
A method according to claim 1 including the step of generating said short addresses by microcode stored in said processor device.
Claim 6
Dependent Claim
17 words
A method according to claim 1 wherein said processor device is a single chip integrated circuit device.
Claim 7
Dependent Claim
37 words
A method according to claim 1 wherein said at least one high order address bit is added to said short address before applying an address of a processor register external to said device to an external bus.
Claim 8
Dependent Claim
193 words
A computer system comprising: a) an execution unit in a processor device for executing instructions; b) a memory external to and accessed by said processor device using addresses of a given length defining a memory space; c) a plurality of processor registers in said computer system, and said processor device having means for accessing said processor registers, said means for accessing including: i) means for generating within said execution unit a short address defining a range of addresses including addresses of all said processor registers, said short address having a number of bits and being shorter than said given length, ii) a processor register within said processor device being accessed using said short address if said short address identifies a processor register within said processor device; iii) a processor register external to said processor device being accessed using said short address without translation plus at least one high order address bit to produce an address of said given length if said short address identifies a processor register external to said processor device, so that said processor register external to the said processor device is mapped in said memory space of said computer system.
Claim 9
Dependent Claim
193 words
A computer system comprising: a) an execution unit in a processor device for executing instructions; b) a memory external to and accessed by said processor device using addresses of a given length defining a memory space; c) a plurality of processor registers in said computer system, and said processor device having means for accessing said processor registers, said means for accessing including: i) means for generating within said execution unit a short address defining a range of addresses including addresses of all said processor registers, said short address having a number of bits and being shorter than said given length, ii) a processor register within said processor device being accessed using said short address if said short address identifies a processor register within said processor device; iii) a processor register external to said processor device being accessed using said short address without translation plus at least one high order address bit to produce an address of said given length if said short address identifies a processor register external to said processor device, so that said processor register external to the said processor device is mapped in said memory space of said computer system.
Claim 10
Dependent Claim
20 words
A system according to claim 7 including means for generating said short addresses by microcode stored in said processor device.
Claim 11
Independent Claim
181 words
A method of operating a computer system comprising the steps of: a) executing instructions in an execution unit in a processor device; b) accessing a memory external to said processor device using addresses of a given length defining a memory space; c) accessing processor registers in said computer system within said memory space, including: i) generating within said processor device a short address defining a range of addresses including addresses of all of said processor registers, said short address including a number of bits and being shorter than said given length; ii) accessing a processor register within said processor device using said short address if said short address identifies a processor register within said processor device; and iii) accessing a processor register external to said processor device using said short address without translation plus at least one high order address bit to produce an address of said given length if said short address identifies a processor register external to said processor device; wherein said processor register external to said processor device is mapped in said memory space of said computer system.
Claim 12
Independent Claim
181 words
A method of operating a computer system comprising the steps of: a) executing instructions in an execution unit in a processor device; b) accessing a memory external to said processor device using addresses of a given length defining a memory space; c) accessing processor registers in said computer system within said memory space, including: i) generating within said processor device a short address defining a range of addresses including addresses of all of said processor registers, said short address including a number of bits and being shorter than said given length; ii) accessing a processor register within said processor device using said short address if said short address identifies a processor register within said processor device; and iii) accessing a processor register external to said processor device using said short address without translation plus at least one high order address bit to produce an address of said given length if said short address identifies a processor register external to said processor device; wherein said processor register external to said processor device is mapped in said memory space of said computer system.
Claim 13
Dependent Claim
21 words
A method according to claim 9 including the step of generating said short addresses by microcode stored in said processor device.
Claim 14
Dependent Claim
300 words
A computer system comprising: a) a single-chip integrated circuit processor device including an instruction execution unit and a micro-control ROM for controlling said instruction execution unit; b) an addressable main memory external to said single-chip integrated circuit processor device; c) a 32-bit wide address bus interconnecting said main memory to said single-chip integrated circuit processor device for permitting said single-chip integrated circuit processor device to address said main memory by using a 32-bit address; d) processor registers external to said single-chip integrated circuit processor device for storing processor state and control information, said processor registers being connected to said 32-bit wide address bus for being addressed by 32-bit addresses on said 32-bit wide address bus; and e) processor registers internal to said single-chip integrated circuit processor device for storing processor state and control information; wherein said micro-control ROM has eight output bits for specifying an eight-bit register address for addressing said processor registers internal to said single-chip integrated circuit processor device and said processor registers external to said single-chip integrated circuit processor device; and wherein said single-chip integrated circuit processor device further includes f) first means for accessing each of said processor registers internal to said single-chip integrated circuit processor device when said eight-bit register address addresses said each of said processor registers internal to said single-chip integrated circuit processor device; and g) second means for accessing each of said processor registers external to said single-chip integrated circuit processor device when said eight-bit register address addresses said each of said processor registers external to said single-chip integrated circuit processor device, said second means for accessing including means for converting said eight-bit register address to a 32-bit address on said 32-bit address bus by adding high-order bits to eight low-order bits which are the eight output bits of said micro-control ROM.
Claim 15
Dependent Claim
300 words
A computer system comprising: a) a single-chip integrated circuit processor device including an instruction execution unit and a micro-control ROM for controlling said instruction execution unit; b) an addressable main memory external to said single-chip integrated circuit processor device; c) a 32-bit wide address bus interconnecting said main memory to said single-chip integrated circuit processor device for permitting said single-chip integrated circuit processor device to address said main memory by using a 32-bit address; d) processor registers external to said single-chip integrated circuit processor device for storing processor state and control information, said processor registers being connected to said 32-bit wide address bus for being addressed by 32-bit addresses on said 32-bit wide address bus; and e) processor registers internal to said single-chip integrated circuit processor device for storing processor state and control information; wherein said micro-control ROM has eight output bits for specifying an eight-bit register address for addressing said processor registers internal to said single-chip integrated circuit processor device and said processor registers external to said single-chip integrated circuit processor device; and wherein said single-chip integrated circuit processor device further includes f) first means for accessing each of said processor registers internal to said single-chip integrated circuit processor device when said eight-bit register address addresses said each of said processor registers internal to said single-chip integrated circuit processor device; and g) second means for accessing each of said processor registers external to said single-chip integrated circuit processor device when said eight-bit register address addresses said each of said processor registers external to said single-chip integrated circuit processor device, said second means for accessing including means for converting said eight-bit register address to a 32-bit address on said 32-bit address bus by adding high-order bits to eight low-order bits which are the eight output bits of said micro-control ROM.
References Cited (Backward Citations)
US4041462A
Cited
US4352157A
Cited
US4236206A
Cited
US4403287A
Cited
US4648035A
Cited
US4649471A
Cited
US4713748A
Cited
US5081574A
Cited
US5109494A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-01 | 1999-07-03 | 2000-01-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-01 | 2003-07-03 | 2004-01-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-01 | 2007-07-03 | 2008-01-02 | $7700.00 | Window Closed / Lapsed |