Area matched package

Claim 1

A chip-scale packaged integrated circuit comprising: a semiconductor die having first and second opposite major die faces and a plurality of die edge faces bounding the major die faces; an integrated circuit formed on the first die face and having a plurality of conductive contact bumps on the first major die face; a rigid carrier having first and second opposite major carrier faces and a plurality of carrier edge faces bounding the major carrier faces, the first major carrier face facing the first major die face; a plurality of I/O contact pads formed on the first major carrier surface in registration with the contact bumps on the first major die face and fused together to form electrical and mechanical connections therebetween; the contact bumps and contact pads being mutually formed to space the first die face and first carrier face a substantially uniform distance apart define a narrow gap therebetween bridged by said connections; and an underfill material filling the gap between the first major faces of the die and carrier around the connections and bonded to said faces to distribute and relieve stresses exerted on the interconnections due to a mismatch of thermal expansion between the die and carrier; the die and carrier being sized and shaped to substantially identical geometric shapes and positioned such that their respective edge faces are aligned to a common plane to form a packaged IC in which the die and carrier have a substantially 1:1 area ratio.